Abstract: A method of controlling, by using a mobile terminal, at least one Bluetooth Low Energy (BLE) device is provided. The method includes searching for at least one BLE device, displaying a BLE device list, including the at least one searched for BLE device, on a display unit of the mobile terminal, receiving an input of selection of a BLE device from the BLE device list, receiving an input of user added information from a user regarding the selected BLE device, and mapping and storing property information and the user added information regarding the selected BLE device.

Abstract: A shoes care device includes an inner cabinet and a module housing. A blowing part, a heating part, and a dehumidifying part are jointly accommodated in a module chamber inside a module housing, and the module housing is detachably coupled to a lower side of the inner cabinet. A shoes care device having a structure in which condensed water generated while passing through the blowing part, the heating part, and/or the dehumidifying part can be prevented from being leaked, and it is advantageous for leakage management, and the module housing and a component accommodated therein are easily managed and replaced.

Abstract: A filter holder comprises: a plurality of filter frames disposed such that at least some thereof are adjacent to each other; and a folding member which supports filter frames, from among the plurality of filter frames, adjacent to each other so as to be rotatable with respect to each other. The folding member comprises: a folding part which has a predetermined thickness and is flexible so as to be foldable by means of rotation of the adjacent filter frames adjacent with respect to each other; and a plurality of edge parts which are connected to the respective sides of the folding part with the folding portion therebetween and rotate together with the adjacent filter frames, and wherein when viewed from a cross-section of the folding member, the edge parts may have a greater thickness than the folding part.

Abstract: An air filter comprises: a first filter frame in which a plurality of first chambers are formed; a second filter frame in which a plurality of second chambers are formed and which is arranged at the rear of the first filter frame; and a filter material which is accommodated in the plurality of first chambers and the plurality of second chambers to filter air, wherein the first filter frame and the second filter frame are arranged so that, when seen from the front, the center of each of the plurality of second chambers is out of line with the center of each of the plurality of first chambers, in the vertical direction.

Abstract: A semiconductor device includes an input control signal generation circuit configured to generate an input control signal when performing an internal operation and configured to adjust a time point at which the input control signal is generated, based on whether a frequency of a clock corresponds to a preset frequency range. The semiconductor device includes an output control signal generation circuit configured to generate an output control signal after a latency elapses when performing the internal operation. The semiconductor device includes a pipe latch circuit configured to latch input data based on the input control signal and configured to output the latched input data as output data based on the output control signal.

Abstract: A semiconductor device includes an input control signal generation circuit configured to generate an input control signal when performing an internal operation and configured to adjust a time point at which the input control signal is generated, based on whether a frequency of a clock corresponds to a preset frequency range. The semiconductor device includes an output control signal generation circuit configured to generate an output control signal after a latency elapses when performing the internal operation. The semiconductor device includes a pipe latch circuit configured to latch input data based on the input control signal and configured to output the latched input data as output data based on the output control signal.

Abstract: A memory device includes a data pad disposed in a first pad area and configured to receive data, a data strobe pad disposed in the first pad area and configured to receive a data strobe signal, a clock pad disposed in a second pad area adjacent to the first pad area and configured to receive a clock signal, a data conversion circuit disposed in the first pad area and configured to convert the data inputted through the data pad into parallel data based on the data strobe signal, and a data driving circuit disposed in the first pad area and configured to transmit the parallel data through a global input and output line based on the clock signal.

Abstract: A memory device includes a data pad disposed in a first pad area and configured to receive data, a data strobe pad disposed in the first pad area and configured to receive a data strobe signal, a clock pad disposed in a second pad area adjacent to the first pad area and configured to receive a clock signal, a data conversion circuit disposed in the first pad area and configured to convert the data inputted through the data pad into parallel data based on the data strobe signal, and a data driving circuit disposed in the first pad area and configured to transmit the parallel data through a global input and output line based on the clock signal.

Abstract: A semiconductor device includes an internal clock generation circuit configured to generate first to fourth internal clocks from first and third divided clocks and a ground voltage in first and second modes. The semiconductor device also includes a data processing circuit configured to latch first to fourth internal data according to first to fourth input control signals. The data processing circuit is additionally configured to generate first to fourth output data by determining the output priority of the latched first and third internal data and the latched second and fourth internal data according to the first to fourth internal clocks, first to fourth rising output control signals, and first to fourth falling output control signals.

Abstract: A semiconductor device includes an internal clock generation circuit configured to generate first to fourth internal clocks from first and third divided clocks and a ground voltage in first and second modes. The semiconductor device also includes a data processing circuit configured to latch first to fourth internal data according to first to fourth input control signals. The data processing circuit is additionally configured to generate first to fourth output data by determining the output priority of the latched first and third internal data and the latched second and fourth internal data according to the first to fourth internal clocks, first to fourth rising output control signals, and first to fourth falling output control signals.