Abstract: A pad is disposed on a substrate. A bump structure is disposed on the pad and electrically connected to the pad. The bump structure includes a first copper layer and a second copper layer sequentially stacked on the pad and a solder ball on the second copper layer. A first X-ray diffraction (XRD) peak intensity ratio of (111) plane to (200) plane of the first copper layer is greater than a second XRD peak intensity ratio of (111) plane to (200) plane of the second copper layer.

Abstract: A semiconductor device can include a substrate that has a surface. A via structure can extend through the substrate toward the surface of the substrate, where the via structure includes an upper surface. A pad structure can be on the surface of the substrate, where the pad structure can include a lower surface having at least one protrusion that is configured to protrude toward the upper surface of the via structure.

Abstract: According to aspects provided herein, a semiconductor device may include a bump providing improved reliability and reduced size. In some aspects, a conductive pad may be formed on a substrate, and a conductive support layer, which may be a pillar, may be formed on the conductive pad. An intermetallic compound (IMC) layer may be formed on the conductive support layer, and a solder layer may be formed on the IMC layer. In some aspects, the conductive support layer may be of a smaller width than the IMC layer. In some aspects, the conductive support layer may have side surfaces which are wider at the solder side than at the conductive pad side. In some aspects, other layers may be formed, such as a seed layer between the conductive pad and the conductive support layer, or a barrier layer between the conductive support layer and the IMC layer.

Abstract: A pad is disposed on a substrate. A bump structure is disposed on the pad and electrically connected to the pad. The bump structure includes a first copper layer and a second copper layer sequentially stacked on the pad and a solder ball on the second copper layer. A first X-ray diffraction (XRD) peak intensity ratio of (111) plane to (200) plane of the first copper layer is greater than a second XRD peak intensity ratio of (111) plane to (200) plane of the second copper layer.

Abstract: An electronic device is provided, which includes a substrate having an electrically conductive contact pad thereon and an electrically conductive connection terminal on the contact pad. The connection terminal includes an electrically conductive pillar structure and a solder layer that extends on the pillar structure and contacts a protruding portion of a sidewall of the pillar structure. The pillar structure can include a lower pillar layer, a diffusion barrier layer on the lower pillar layer and an upper pillar layer on the diffusion barrier layer. In some additional embodiments of the invention, the protruding portion of the sidewall of the pillar structure includes an outermost portion of an upper surface of the diffusion barrier layer. This can be achieved by making a width of the diffusion barrier layer greater than a width of the upper pillar layer when viewed in transverse cross-section.

Abstract: An integrated circuit device includes a semiconductor structure, a through-silicon-via (TSV) structure that penetrates through the semiconductor structure and a connection terminal connected to the TSV structure. A metal capping layer includes a flat capping portion that covers the bottom surface of the connection terminal and a wedge-shaped capping portion that is integrally connected to the flat capping portion and that partially covers a side wall of the connection terminal. The metal capping layer may be formed by an electroplating process in which the connection terminal is in contact with a metal strike electroplating solution while a pulse-type current is applied.

Abstract: A semiconductor device includes a via structure penetrating through a substrate, a portion of the via structure being exposed over a surface of the substrate, a protection layer pattern structure provided on the surface of the substrate and including a first protection layer pattern and a second protection layer pattern, the first protection layer pattern surrounding a lower sidewall of the exposed portion of the via structure and exposing an upper sidewall of the exposed portion of the via structure, the second protection layer pattern exposing a portion of the top surface of the first protection layer pattern adjacent to the sidewall of the via structure, and a pad structure provided on the via structure and the protection layer pattern structure and covering the top surface of the first protection layer pattern exposed by the second protection layer pattern.

Abstract: According to aspects provided herein, a semiconductor device may include a bump providing improved reliability and reduced size. In some aspects, a conductive pad may be formed on a substrate, and a conductive support layer, which may be a pillar, may be formed on the conductive pad. An intermetallic compound (IMC) layer may be formed on the conductive support layer, and a solder layer may be formed on the IMC layer. In some aspects, the conductive support layer may be of a smaller width than the IMC layer. In some aspects, the conductive support layer may have side surfaces which are wider at the solder side than at the conductive pad side. In some aspects, other layers may be formed, such as a seed layer between the conductive pad and the conductive support layer, or a barrier layer between the conductive support layer and the IMC layer.

Abstract: A semiconductor device having a chip stack and an interconnection terminal is provided. The chip stack includes a first semiconductor chip, a second semiconductor chip and a third semiconductor chip stacked on each other. The interconnection terminal is electrically coupled to the chip stack. The first semiconductor chip includes a first front surface and a first backside surface. The second semiconductor chip includes a second front surface, a second backside surface, a second circuit layer and a through-electrode which is electrically coupled to the second circuit layer and penetrates the second semiconductor chip. The third semiconductor chip includes a third front surface, a third backside surface opposite to the third front surface and a third circuit layer adjacent to the third front surface. The first front surface and the second front surface face each other. The third front surface and the second backside surface face each other.

Abstract: An electronic device is provided, which includes a substrate having an electrically conductive contact pad thereon and an electrically conductive connection terminal on the contact pad. The connection terminal includes an electrically conductive pillar structure and a solder layer that extends on the pillar structure and contacts a protruding portion of a sidewall of the pillar structure. The pillar structure can include a lower pillar layer, a diffusion barrier layer on the lower pillar layer and an upper pillar layer on the diffusion barrier layer. In some additional embodiments of the invention, the protruding portion of the sidewall of the pillar structure includes an outermost portion of an upper surface of the diffusion barrier layer. This can be achieved by making a width of the diffusion barrier layer greater than a width of the upper pillar layer when viewed in transverse cross-section.

Abstract: Methods for fabricating semiconductor devices having through electrodes are provided. The method may comprise forming a via hole which opens towards an upper surface of a substrate and disconnects with a lower surface of the substrate; forming a via isolation layer which extends along an inner surface of the via hole and covers the upper surface of the substrate; forming a seed layer on the via isolation layer which extends along the via isolation layer; annealing the seed layer in-situ after forming the seed layer; forming a conductive layer, filling the via hole, by an electroplating using the seed layer; and planarizing the upper surface of the substrate to form a through electrode surrounded by the via isolation layer in the via hole.

Abstract: A semiconductor device having a chip stack and an interconnection terminal is provided. The chip stack includes a first semiconductor chip, a second semiconductor chip and a third semiconductor chip stacked on each other. The interconnection terminal is electrically coupled to the chip stack. The first semiconductor chip includes a first front surface and a first backside surface. The second semiconductor chip includes a second front surface, a second backside surface, a second circuit layer and a through-electrode which is electrically coupled to the second circuit layer and penetrates the second semiconductor chip. The third semiconductor chip includes a third front surface, a third backside surface opposite to the third front surface and a third circuit layer adjacent to the third front surface. The first front surface and the second front surface face each other. The third front surface and the second backside surface face each other.

Abstract: A wafer-to-wafer bonding structure may include: a first wafer including a first insulating layer on a first substrate and on a first copper (Cu) pad that penetrates the first insulating layer and has portions protruding from an upper surface of the first insulating layer, and a first barrier metal layer on a lower surface and sides of the first Cu pad; a second wafer including a second insulating layer on a second substrate and on a second copper (Cu) pad that penetrates the second insulating layer, has portions protruding from an upper surface of the second insulating layer, and is bonded to the first Cu pad, and a second barrier metal layer on a lower surface and sides of the second Cu pad; and a polymer layer covering protruding sides of the first and second barrier metal layers and disposed between the first and second wafers.

Abstract: An integrated circuit device includes a semiconductor structure, a through-silicon-via (TSV) structure that penetrates through the semiconductor structure and a connection terminal connected to the TSV structure. A metal capping layer includes a flat capping portion that covers the bottom surface of the connection terminal and a wedge-shaped capping portion that is integrally connected to the flat capping portion and that partially covers a side wall of the connection terminal. The metal capping layer may be formed by an electroplating process in which the connection terminal is in contact with a metal strike electroplating solution while a pulse-type current is applied.

Abstract: A semiconductor device can include a substrate that has a surface. A via structure can extend through the substrate toward the surface of the substrate, where the via structure includes an upper surface. A pad structure can be on the surface of the substrate, where the pad structure can include a lower surface having at least one protrusion that is configured to protrude toward the upper surface of the via structure.

Abstract: A wafer-to-wafer bonding structure may include: a first wafer including a first insulating layer on a first substrate and on a first copper (Cu) pad that penetrates the first insulating layer and has portions protruding from an upper surface of the first insulating layer, and a first barrier metal layer on a lower surface and sides of the first Cu pad; a second wafer including a second insulating layer on a second substrate and on a second copper (Cu) pad that penetrates the second insulating layer, has portions protruding from an upper surface of the second insulating layer, and is bonded to the first Cu pad, and a second barrier metal layer on a lower surface and sides of the second Cu pad; and a polymer layer covering protruding sides of the first and second barrier metal layers and disposed between the first and second wafers.

Abstract: Methods of forming an integrated circuit device include forming an interlayer dielectric layer on a first surface of a semiconductor substrate and then forming an interconnect hole that extends through the interlayer dielectric layer and into the semiconductor substrate. A first sidewall spacer layer is formed on a sidewall of the interconnect hole. The semiconductor substrate at a bottom of the interconnect hole is isotropically etched to define an undercut recess in the semiconductor substrate. This etching step is performed using the first sidewall spacer layer as an etching mask. The interconnect hole and the uncut recess are then filled with a through-via electrode. A second surface of the semiconductor substrate is removed for a sufficient duration to expose the uncut recess containing the through-via electrode.

Abstract: A semiconductor device having a chip stack and an interconnection terminal is provided. The chip stack includes a first semiconductor chip, a second semiconductor chip and a third semiconductor chip stacked on each other. The interconnection terminal is electrically coupled to the chip stack. The first semiconductor chip includes a first front surface and a first backside surface. The second semiconductor chip includes a second front surface, a second backside surface, a second circuit layer and a through-electrode which is electrically coupled to the second circuit layer and penetrates the second semiconductor chip. The third semiconductor chip includes a third front surface, a third backside surface opposite to the third front surface and a third circuit layer adjacent to the third front surface. The first front surface and the second front surface face each other. The third front surface and the second backside surface face each other.

Abstract: The inventive concept provides methods for inhibiting the formation of one or more oxides on metal bumps during the formation of solder joint structures and solder joint structures including one or more preservative films. In some embodiments, the solder joint structure includes a metal bump having a preservative film disposed on the surface thereof.

Abstract: An integrated circuit (IC) device includes a semiconductor substrate having a via hole extending through at least a part thereof, a conductive structure in the via hole, a conductive barrier layer adjacent the conductive structure; and a via insulating layer interposed between the semiconductor substrate and the conductive barrier layer. The conductive barrier layer may include an outer portion oxidized between the conductive barrier layer and the via insulating layer, and the oxidized outer portion of the conductive barrier layer may substantially surrounds the remaining portion of the conductive barrier layer.