Patents by Inventor Ju-seok Maeng

Ju-seok Maeng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6618642
    Abstract: A method, apparatus and program storage device for analyzing and optimizing equipment efficiency are disclosed. In an illustrative embodiment equipment running time is subdivided into a valuable operating time component and a plurality of performance loss time components. Ideal equipment reference information reflecting dynamic manufacturing parameters is simulated, and an operational performance loss is analyzed in detail. From the analysis of the operational performance loss, priority in input of resources is determined. Advantageously, parameters of a dynamically changing manufacturing environment are incorporated in the analysis and optimization of general equipment efficiency. Moreover, performance loss is more accurately analyzed compared to conventional methods. As such, the performance operating rate is more effectively utilized in reducing performance loss.
    Type: Grant
    Filed: December 13, 2000
    Date of Patent: September 9, 2003
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ju-Seok Maeng, In-ho Hyun, Sung-tae Kim
  • Patent number: 6563331
    Abstract: An apparatus for testing semiconductor devices allows various testing processes, including a burn-in process, to be performed at the same testing stage. Test trays which contain the semiconductor devices are used throughout an in-line system so that an entire back-end process can be performed without loading/unloading the semiconductor devices between the various tests. The in-line system includes multiple test and burn-in apparatuses as well as a single sorting unit which performs a composite sorting operation after all the testing processes. A method for testing semiconductor devices in the in-line system includes testing the semiconductor devices in the test trays using the test and burn-in apparatus, transferring the test trays to a different testing apparatus for a second testing, and finally sorting the semiconductor devices after all testing processes have been performed based on a final sorting map created by combining test tray maps generated during each of the tests.
    Type: Grant
    Filed: August 21, 2001
    Date of Patent: May 13, 2003
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Ju Seok Maeng
  • Patent number: 6313652
    Abstract: A test and burn-in apparatus for semiconductor chip package devices, an in-line system which includes the test and burn-in apparatus, and a test method which employs the in-line system are provided. A test and burn-in apparatus for testing semiconductor devices allows various testing processes, including a burn-in process, to be performed at the same testing stage. The apparatus employs test trays which contain the semiconductor devices. These test trays are used throughout the in-line system so that an entire back-end process can be performed without the need for loading/unloading the semiconductor devices into and from device trays between the various tests. The test and burn-in apparatus according to this invention can therefore occupy less space than the prior art testing apparatuses. The in-line system includes multiple test and burn-in apparatuses as well as a single sorting unit which performs a composite sorting operation after all the testing processes have been performed.
    Type: Grant
    Filed: December 22, 1998
    Date of Patent: November 6, 2001
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Ju Seok Maeng
  • Patent number: 6287878
    Abstract: A chip scale package (CSP) fabricating method is provided. In this method, CSP chips are fabricated on a wafer and subjected to an electric die sorting (EDS) process. Then, CSP chips determined to be non-defective through the FDS process are packaged into a CSP strip. and the CSP strip is subjected to a final test. Then, the CSP strip subjected to the final test is singulated into individual CSPs. Following this, the CSPs are surface-mounted on a module board. Substantially all of the CSPs on the CSP module board are subsequently burn-in tested. As a result, productivity is improved, and manufacturing costs are reduced.
    Type: Grant
    Filed: July 20, 2000
    Date of Patent: September 11, 2001
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ju-seok Maeng, In-ho Hyun
  • Publication number: 20010005799
    Abstract: A method, apparatus and program storage device for analyzing and optimizing equipment efficiency are disclosed. In an illustrative embodiment equipment running time is subdivided into a valuable operating time component and a plurality of performance loss time components. Ideal equipment reference information reflecting dynamic manufacturing parameters is simulated, and an operational performance loss is analyzed in detail. From the analysis of the operational performance loss, priority in input of resources is determined. Advantageously, parameters of a dynamically changing manufacturing environment are incorporated in the analysis and optimization of general equipment efficiency. Moreover, performance loss is more accurately analyzed compared to conventional methods. As such, the performance operating rate is more effectively utilized in reducing performance loss.
    Type: Application
    Filed: December 13, 2000
    Publication date: June 28, 2001
    Inventors: Ju-seok Maeng, In-ho Hyun, Sung-tae Kim