Patents by Inventor Juan Guillermo Revilla
Juan Guillermo Revilla has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 6851041Abstract: A pipelined data processing unit includes an instruction sequencer and n functional units capable of executing n operations in parallel. The instruction sequencer includes a random access memory for storing very-long-instruction-words (VLIWs) used in operations involving the execution of two or more functional units in parallel. Each VLIW comprises a plurality of short-instruction-words (SIWs) where each SIW corresponds to a unique type of instruction associated with a unique functional unit. VLIWs are composed in the VLIW memory by loading and concatenating SIWs in each address, or entry. VLIWs are executed via the execute-VLIW (XV) instruction. The iVLIWs can be compressed at a VLIW memory address by use of a mask field contained within the XV1 instruction which specifies which functional units are enabled, or disabled, during the execution of the VLIW. The mask can be changed each time the XV1 instruction is executed, effectively modifying the VLIW every time it is executed.Type: GrantFiled: September 24, 2002Date of Patent: February 1, 2005Assignee: PTS CorporationInventors: Gerald G. Pechanek, Juan Guillermo Revilla, Edwin Franklin Barry
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Patent number: 6848041Abstract: A hierarchical instruction set architecture (ISA) provides pluggable instruction set capability and support of array processors. The term pluggable is from the programmer's viewpoint and relates to groups of instructions that can easily be added to a processor architecture for code density and performance enhancements. One specific aspect addressed herein is the unique compacted instruction set which allows the programmer the ability to dynamically create a set of compacted instructions on a task by task basis for the primary purpose of improving control and parallel code density. These compacted instructions are parallelizable in that they are not specifically restricted to control code application but can be executed in the processing elements (PEs) in an array processor. The ManArray family of processors is designed for this dynamic compacted instruction set capability and also supports a scalable array of from one to N PEs.Type: GrantFiled: April 28, 2003Date of Patent: January 25, 2005Assignee: PTS CorporationInventors: Gerald G. Pechanek, Edwin F. Barry, Juan Guillermo Revilla, Larry D. Larsen
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Patent number: 6775766Abstract: A ManArray processor pipeline design addresses an indirect VLIW memory access problem without increasing branch latency by providing a dynamically reconfigurable instruction pipeline for SIWs requiring a VLIW to be fetched. By introducing an additional cycle in the pipeline only when a VLIW fetch is required, the present invention solves the VLIW memory access problem. The pipeline stays in an expanded state, in general, until a branch type or load VLIW memory type operation is detected returning the pipeline to a compressed pipeline operation. By compressing the pipeline when a branch type operation is detected, the need for an additional cycle for the branch operation is avoided. Consequently, the shorter compressed pipeline provides more efficient performance for branch intensive control code as compared to a fixed pipeline with an expanded number of pipeline stages.Type: GrantFiled: February 28, 2001Date of Patent: August 10, 2004Assignee: PTS CorporationInventors: Juan Guillermo Revilla, Edwin F. Barry, Patrick Rene Marchand, Gerald G. Pechanek
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Publication number: 20030200420Abstract: A hierarchical instruction set architecture (ISA) provides pluggable instruction set capability and support of array processors. The term pluggable is from the programmer's viewpoint and relates to groups of instructions that can easily be added to a processor architecture for code density and performance enhancements. One specific aspect addressed herein is the unique compacted instruction set which allows the programmer the ability to dynamically create a set of compacted instructions on a task by task basis for the primary purpose of improving control and parallel code density. These compacted instructions are parallelizable in that they are not specifically restricted to control code application but can be executed in the processing elements (PEs) in an array processor. The ManArray family of processors is designed for this dynamic compacted instruction set capability and also supports a scalable array of from one to N PEs.Type: ApplicationFiled: April 28, 2003Publication date: October 23, 2003Applicant: PTS CorporationInventors: Gerald G. Pechanek, Edwin F. Barry, Juan Guillermo Revilla, Larry D. Larsen
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Patent number: 6557094Abstract: A hierarchical instruction set architecture (ISA) provides pluggable instruction set capability and support of array processors. The term pluggable is from the programmer's viewpoint and relates to groups of instructions that can easily be added to a processor architecture for code density and performance enhancements. One specific aspect addressed herein is the unique compacted instruction set which allows the programmer the ability to dynamically create a set of compacted instructions on a task by task basis for the primary purpose of improving control and parallel code density. These compacted instructions are parallelizable in that they are not specifically restricted to control code application but can be executed in the processing elements (PEs) in an array processor. The ManArray family of processors is designed for this dynamic compacted instruction set capability and also supports a scalable array of from one to N PEs.Type: GrantFiled: September 28, 2001Date of Patent: April 29, 2003Assignee: Bops, Inc.Inventors: Gerald G. Pechanek, Edwin F. Barry, Juan Guillermo Revilla, Larry D. Larsen
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Publication number: 20030079109Abstract: A pipelined data processing unit includes an instruction sequencer and n functional units capable of executing n operations in parallel. The instruction sequencer includes a random access memory for storing very-long-instruction-words (VLIWs) used in operations involving the execution of two or more functional units in parallel. Each VLIW comprises a plurality of short-instruction-words (SIWs) where each SIW corresponds to a unique type of instruction associated with a unique functional unit. VLIWs are composed in the VLIW memory by loading and concatenating SIWs in each address, or entry. VLIWs are executed via the execute-VLIW (XV) instruction. The iVLIWs can be compressed at a VLIW memory address by use of a mask field contained within the XV1 instruction which specifies which functional units are enabled, or disabled, during the execution of the VLIW. The mask can be changed each time the XV1 instruction is executed, effectively modifying the VLIW every time it is executed.Type: ApplicationFiled: September 24, 2002Publication date: April 24, 2003Applicant: BOPS, Inc.Inventors: Gerald G. Pechanek, Juan Guillermo Revilla, Edwin F. Barry
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Publication number: 20030061473Abstract: A ManArray processor pipeline design addresses an indirect VLIW memory access problem without increasing branch latency by providing a dynamically reconfigurable instruction pipeline for SIWs requiring a VLIW to be fetched. By introducing an additional cycle in the pipeline only when a VLIW fetch is required, the present invention solves the VLIW memory access problem. The pipeline stays in an expanded state, in general, until a branch type or load VLIW memory type operation is detected returning the pipeline to a compressed pipeline operation. By compressing the pipeline when a branch type operation is detected, the need for an additional cycle for the branch operation is avoided. Consequently, the shorter compressed pipeline provides more efficient performance for branch intensive control code as compared to a fixed pipeline with an expanded number of pipeline stages.Type: ApplicationFiled: February 28, 2001Publication date: March 27, 2003Inventors: Juan Guillermo Revilla, Edwin F. Barry, Patrick Rene Marchand, Gerald G. Pechanek
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Patent number: 6467036Abstract: A pipelined data processing unit includes an instruction sequencer and n functional units capable of executing n operations in parallel. The instruction sequencer includes a random access memory for storing very-long-instruction-words (VLIWs) used in operations involving the execution of two or more functional units in parallel. Each VLIW comprises a plurality of short-instruction-words (SIWs) where each SIW corresponds to a unique type of instruction associated with a unique functional unit. VLIWs are composed in the VLIW memory by loading and concatenating SIWs in each address, or entry. VLIWs are executed via the execute-VLIW (XV) instruction. The iVLIWs can be compressed at a VLIW memory address by use of a mask field contained within the XV1 instruction which specifies which functional units are enabled, or disabled, during the execution of the VLIW. The mask can be changed each time the XV1 instruction is executed, effectively modifying the VLIW every time it is executed.Type: GrantFiled: November 21, 2000Date of Patent: October 15, 2002Assignee: BOPS, Inc.Inventors: Gerald G. Pechanek, Juan Guillermo Revilla, Edwin F. Barry
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Patent number: 6460120Abstract: A network switch apparatus, components for such an apparatus, and methods of operating such an apparatus in which data flow handling and flexibility is enhanced by the cooperation of a plurality of memory elements and a plurality of interface processors formed on a semiconductor substrate. The memory elements and interface processors together form a network processor capable of cooperating with other elements in executing instructions directing the flow of data in a network. Access to the memory elements is controlled in a particular manner and under operative rules which provide controlled multiple accesses of the plurality of memory elements by the plurality of processors.Type: GrantFiled: August 27, 1999Date of Patent: October 1, 2002Assignee: International Business Machines CorporationInventors: Brian Mitchell Bass, Jean Louis Calvignac, Marco C. Heddes, Piyush Chunilal Patel, Juan Guillermo Revilla, Michael Steven Siegel, Fabrice Jean Verplanken
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Patent number: 6446191Abstract: A SIMD machine employing a plurality of parallel processor (PEs) in which communications hazards are eliminated in an efficient manner. An indirect Very Long Instruction Word instruction memory (VIM) is employed along with execute and delimiter instructions. A masking mechanism may be employed to control which PEs have their VIMs loaded. Further, a receive model of operation is preferably employed. In one aspect, each PE operates to control a switch that selects from which PE it receives. The present invention addresses a better machine organization for execution of parallel algorithms that reduces hardware cost and complexity while maintaining the best characteristics of both SIMD and MIMD machines and minimizing communication latency. This invention brings a level of MIMD computational autonomy to SIMD indirect Very Long Instruction Word (iVLIW) processing elements while maintaining the single thread of control used in the SIMD machine organization.Type: GrantFiled: October 2, 2000Date of Patent: September 3, 2002Assignee: BOPS, Inc.Inventors: Gerald G. Pechanek, Thomas L. Drabenstott, Juan Guillermo Revilla, David Carl Strube, Grayson Morris
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Publication number: 20020099855Abstract: A network switch apparatus, components for such an apparatus, and methods of operating such an apparatus in which data flow handling and flexibility is enhanced by the cooperation of a plurality of memory elements and a plurality of interface processors formed on a semiconductor substrate. The memory elements and interface processors together form a network processor capable of cooperating with other elements in executing instructions directing the flow of data in a network. Access to the memory elements is controlled in a particular manner and under operative rules which provide controlled multiple accesses of the plurality of memory elements by the plurality of processors.Type: ApplicationFiled: August 27, 1999Publication date: July 25, 2002Inventors: BRIAN MITCHELL BASS, MARCO C. HEDDES, PIYUSH CHUNILAL PATEL, JUAN GUILLERMO REVILLA, MICHAEL STEVEN SIEGEL, FABRICE JEAN VERPLANKEN
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Publication number: 20020073299Abstract: A hierarchical instruction set architecture (ISA) provides pluggable instruction set capability and support of array processors. The term pluggable is from the programmer's viewpoint and relates to groups of instructions that can easily be added to a processor architecture for code density and performance enhancements. One specific aspect addressed herein is the unique compacted instruction set which allows the programmer the ability to dynamically create a set of compacted instructions on a task by task basis for the primary purpose of improving control and parallel code density. These compacted instructions are parallelizable in that they are not specifically restricted to control code application but can be executed in the processing elements (PEs) in an array processor. The ManArray family of processors is designed for this dynamic compacted instruction set capability and also supports a scalable array of from one to N PEs.Type: ApplicationFiled: September 28, 2001Publication date: June 13, 2002Inventors: Gerald G. Pechanek, Edwin F. Barry, Juan Guillermo Revilla, Larry D. Larsen
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Patent number: 6321322Abstract: A hierarchical instruction set architecture (ISA) provides pluggable instruction set capability and support of array processors. The term pluggable is from the programmer's viewpoint and relates to groups of instructions that can easily be added to a processor architecture for code density and performance enhancements. One specific aspect addressed herein is the unique compacted instruction set which allows the programmer the ability to dynamically create a set of compacted instructions on a task by task basis for the primary purpose of improving control and parallel code density. These compacted instructions are parallelizable in that they are not specifically restricted to control code application but can be executed in the processing elements (PEs) in an array processor. The ManArray family of processors is designed for this dynamic compacted instruction set capability and also supports a scalable array of from one to N PEs.Type: GrantFiled: April 5, 2000Date of Patent: November 20, 2001Assignee: BOPS, Inc.Inventors: Gerald G. Pechanek, Edwin F. Barry, Juan Guillermo Revilla, Larry D. Larsen
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Patent number: 6216223Abstract: A ManArray processor pipeline design addresses an indirect VLIW memory access problem without increasing branch latency by providing a dynamically reconfigurable instruction pipeline for SIWs requiring a VLIW to be fetched. By introducing an additional cycle in the pipeline only when a VLIW fetch is required, the present invention solves the VLIW memory access problem. The pipeline stays in an expanded state, in general, until a branch type or load VLIW memory type operation is detected returning the pipeline to a compressed pipeline operation. By compressing the pipeline when a branch type operation is detected, the need for an additional cycle for the branch operation is avoided. Consequently, the shorter compressed pipeline provides more efficient performance for branch intensive control code as compared to a fixed pipeline with an expanded number of pipeline stages.Type: GrantFiled: January 12, 1999Date of Patent: April 10, 2001Assignee: Billions of Operations Per Second, Inc.Inventors: Juan Guillermo Revilla, Edwin F. Barry, Patrick Rene Marchand, Gerald G. Pechanek
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Patent number: 6173389Abstract: A pipelined data processing unit includes an instruction sequencer and n functional units capable of executing n operations in parallel. The instruction sequencer includes a random access memory for storing very-long-instruction-words (VLIWs) used in operations involving the execution of two or more functional units in parallel. Each VLIW comprises a plurality of short-instruction-words (SIWs) where each SIW corresponds to a unique type of instruction associated with a unique functional unit. VLIWs are composed in the VLIW memory by loading and concatenating SIWs in each address, or entry. VLIWs are executed via the execute-VLIW (XV) instruction. The iVLIWs can be compressed at a VLIW memory address by use of a mask field contained within the XV1 instruction which specifics which functional units are enabled, or disabled, during the execution of the VLIW. The mask can be changed each time the XV1 instruction is executed, effectively modifying the VLIW every time it is executed.Type: GrantFiled: December 4, 1998Date of Patent: January 9, 2001Assignee: Billions of Operations Per Second, Inc.Inventors: Gerald G. Pechanek, Juan Guillermo Revilla, Edwin F. Barry
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Patent number: 6151668Abstract: A SIMD machine employing a plurality of parallel processor (PEs) in which communications hazards are eliminated in an efficient manner. An indirect Very Long Instruction Word instruction memory (VIM) is employed along with execute and delimiter instructions. A masking mechanism may be employed to control which PEs have their VIMs loaded. Further, a receive model of operation is preferably employed. In one aspect, each PE operates to control a switch that selects from which PE it receives. The present invention addresses a better machine organization for execution of parallel algorithms that reduces hardware cost and complexity while maintaining the best characteristics of both SIMD and MIMD machines and minimizing communication latency. This invention brings a level of MIMD computational autonomy to SIMD indirect Very Long Instruction Word (iVLIW) processing elements while maintaining the single thread of control used in the SIMD machine organization.Type: GrantFiled: November 6, 1998Date of Patent: November 21, 2000Assignee: Billions of Operations Per Second, Inc.Inventors: Gerald G. Pechanek, Thomas L. Drabenstott, Juan Guillermo Revilla, David Carl Strube, Grayson Morris
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Patent number: 6101592Abstract: A hierarchical instruction set architecture (ISA) provides pluggable instruction set capability and support of array processors. The term pluggable is from the programmer's viewpoint and relates to groups of instructions that can easily be added to a processor architecture for code density and performance enhancements. One specific aspect addressed herein is the unique compacted instruction set which allows the programmer the ability to dynamically create a set of compacted instructions on a task by task basis for the primary purpose of improving control and parallel code density. These compacted instructions are parallelizable in that they are not specifically restricted to control code application but can be executed in the processing elements (PEs) in an array processor. The ManArray family of processors is designed for this dynamic compacted instruction set capability and also supports a scalable array of from one to N PEs.Type: GrantFiled: December 18, 1998Date of Patent: August 8, 2000Assignee: Billions of Operations Per Second, Inc.Inventors: Gerald G. Pechanek, Edwin F. Barry, Juan Guillermo Revilla, Larry D. Larsen
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Patent number: 6081860Abstract: A process and system for transferring data including at least one slave device connected to at least one master device through an arbiter device. The master and slave devices are connected by a single address bus, a write data bus and a read data bus. The arbiter device receives requests for data transfers from the master devices and selectively transmits the requests to the slave devices. The master devices and the slave devices are further connected by a plurality of transfer qualifier signals which may specify predetermined characteristics of the requested data transfers. Control signals are also communicated between the arbiter device and the slave devices to allow appropriate slave devices to latch addresses of requested second transfers during the pendency of current or primary data transfers so as to obviate an address transfer latency typically required for the second transfer.Type: GrantFiled: November 20, 1997Date of Patent: June 27, 2000Assignee: International Business Machines CorporationInventors: Jeffrey Todd Bridges, Juan Guillermo Revilla, Thomas Andrew Sartorius, Mark Michael Schaffer
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Patent number: 5926831Abstract: A dynamically configured memory controller to prevent speculative memory accesses of non-well behaved memory. Such dynamic configuration of a memory controller may be accomplished by providing to the memory controller guard information associated with memory requests. The memory controller may then prevent speculative memory accesses when the guard information indicates that the memory requests are of non-well behaved memory. The guard information provided to the memory controller may include guard information associated with each memory request provided to the memory controller.Type: GrantFiled: October 11, 1996Date of Patent: July 20, 1999Assignee: International Business Machines CorporationInventors: Juan Guillermo Revilla, Thomas Andrew Sartorius, Mark Michael Schaffer, James N. Dieffenderfer
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Patent number: RE41703Abstract: A SIMD machine employing a plurality of parallel processor (PEs) in which communications hazards are eliminated in an efficient manner. An indirect Very Long Instruction Word instruction memory (VIM) is employed along with execute and delimiter instructions. A masking mechanism may be employed to control which PEs have their VIMs loaded. Further, a receive model of operation is preferably employed. In one aspect, each PE operates to control a switch that selects from which PE it receives. The present invention addresses a better machine organization for execution of parallel algorithms that reduces hardware cost and complexity while maintaining the best characteristics of both SIMD and MIMD machines and minimizing communication latency. This invention brings a level of MIMD computational autonomy to SIMD indirect Very Long Instruction Word (iVLIW) processing elements while maintaining the single thread of control used in the SIMD machine organization.Type: GrantFiled: June 21, 2004Date of Patent: September 14, 2010Assignee: Altera Corp.Inventors: Gerald George Pechanek, Thomas L. Drabenstott, Juan Guillermo Revilla, David Strube, Grayson Morris