Abstract: In the field of transplant rejection, identified are SNPs wherein mismatches in variants present in a recipient and donor for such SNPs are predictive of transplant outcome, wherein the SNPs represent non-HLA loci newly implicated in rejection. By the invention, transplant outcomes such as elevated risk of antibody mediated rejection, elevated risk of T-cell mediated rejection, or low risk of rejection can be predicted by analyzing mismatches between donor and recipient for the enumerated SNPs. Certain SNPs enumerated are predictive of kidney transplant outcome. The compatibility of prospective donors can be assessed for a recipient, allowing for optimized donor-recipient pairing.

Abstract: In the field of transplant rejection, identified are SNPs wherein mismatches in variants present in a recipient and donor for such SNPs are predictive of transplant outcome, wherein the SNPs represent non-HLA loci newly implicated in rejection. By the invention, transplant outcomes such as elevated risk of antibody mediated rejection, elevated risk of T-cell mediated rejection, or low risk of rejection can be predicted by analyzing mismatches between donor and recipient for the enumerated SNPs. Certain SNPs enumerated are predictive of kidney transplant outcome. The compatibility of prospective donors can be assessed for a recipient, allowing for optimized donor-recipient pairing.

Abstract: A fast and efficient implementation of the inverse discrete cosine transform (IDCT). The disclosed IDCT processor achieves a good balance between efficient VLSI implementation and number of needed arithmetic operations and is thus particularly useful in real-time speech and video decompression applications. A standard IDCT computation is modified by factoring an IDCT formula into two parts: a prescaling of each input value followed by a multiplication with a matrix specially chosen so that the product will represent the IDCT of the input data. The premultiply constants are chosen so that the specially chosen matrix has a limited number of distinct values. The VLSI implementation of the matrix multiplication is thus greatly simplified.

Abstract: A DRAM is operated based upon an external clock input, a column enable, and a row enable. The DRAM is accessed and row and column addresses are latched into buffers based upon the clock input.

Abstract: In a display system for a data processing system color words for display at sequential pixels are obtained by addressing a lookup table memory with addresses obtained from a bit map display memory. Initialization data is stored in the display memory and, during an initialization procedure, is applied to the lookup table along the same data path used by the addresses during display. In one system a multiplexer takes the form of a shift register into which sequential pixel addresses are applied in parallel to interleaved stages. The two LUT addresses are read out sequentially by shifting the shift register. During the initialization procedure shifting is disabled and the interleaved address and data bytes are applied along separate address and data lines to the lookup table. One data path can be utilized for either eight plane or four plane display.