Abstract: Technology is described for identifying non-volatile memory cells having data that should be refreshed. The technology could be used to identify which groups of memory cells that store cold data should have a data refresh. In one aspect, a non-volatile storage device has at least one monitor memory cell associated with a group of data memory cells. The non-volatile storage device may use different programming techniques to program the data and monitor memory cells. In one aspect, the programming technique used for the monitor memory cell is less stable with respect to state than the technique used to program the associated data memory cells. The state of the monitor memory cell may change in a predictable manner, such that the state of the monitor cell may be sensed periodically to determine whether the associated data memory cells should be refreshed.

Abstract: A method is provided that includes forming a word line above a substrate, the word line disposed in a first direction, forming a bit line above the substrate, the bit line disposed in a second direction perpendicular to the first direction, forming a nonvolatile memory material between the word line and the bit line, the nonvolatile memory material including a semiconductor material layer and conductive oxide material layer, forming a first barrier material layer between the word line and the nonvolatile memory material, forming a second barrier material layer between the bit line and the nonvolatile memory material, and forming a memory cell including the nonvolatile memory material at an intersection of the bit line and the word line.

Abstract: A method is provided that includes forming a word line above a substrate, the word line disposed in a first direction, forming a bit line above the substrate, the bit line disposed in a second direction perpendicular to the first direction, forming a nonvolatile memory material between the word line and the bit line, and forming a memory cell including the nonvolatile memory material at an intersection of the bit line and the word line. The word line includes a first portion and a second portion including an electrically conductive carbon-containing material. The nonvolatile memory material includes a semiconductor material layer and a conductive oxide material layer, with the semiconductor material layer disposed adjacent the second portion of the word line.

Abstract: A method of operating a resistive memory device includes providing a resistive memory device including an array of resistive memory cells, where each of the resistive memory cells includes a resistive memory material having at least two different resistive states, performing a first mode read operation on a group of resistive memory cells within the array, determining a bit error rate for data generated by the first mode read operation, determining whether the determined bit error rate is below a predetermined limit, and performing a second mode read operation on the group of resistive memory cells within the array based on a threshold voltage if the determined bit error rate is above the predetermined limit.

Abstract: A method of operating a resistive memory device includes providing a resistive memory device including an array of resistive memory cells, where each of the resistive memory cells includes a resistive memory material having at least two different resistive states, performing a first mode read operation on a group of resistive memory cells within the array, determining a bit error rate for data generated by the first mode read operation, determining whether the determined bit error rate is below a predetermined limit, and performing a second mode read operation on the group of resistive memory cells within the array based on a threshold voltage if the determined bit error rate is above the predetermined limit.

Abstract: Technology is described for identifying non-volatile memory cells having data that should be refreshed. The technology could be used to identify which groups of memory cells that store cold data should have a data refresh. In one aspect, a non-volatile storage device has at least one monitor memory cell associated with a group of data memory cells. The non-volatile storage device may use different programming techniques to program the data and monitor memory cells. In one aspect, the programming technique used for the monitor memory cell is less stable with respect to state than the technique used to program the associated data memory cells. The state of the monitor memory cell may change in a predictable manner, such that the state of the monitor cell may be sensed periodically to determine whether the associated data memory cells should be refreshed.

Abstract: Systems and methods for providing a Barrier Modulated Cell (BMC) structure with reduced shifting in stored memory cell resistance levels over time are described. The BMC structure may comprise a reversible resistance-switching memory element within a memory array comprising a first conductive metal oxide (e.g., titanium oxide) in series with an alternating stack of one or more layers of an amorphous low bandgap material (e.g., germanium) with one or more layers of a second conductive metal oxide (e.g., aluminum oxide). The BMC structure may include a barrier layer comprising a first conductive metal oxide, such as titanium oxide or strontium titanate, in series with a germanium stack that includes a layer of amorphous germanium or amorphous silicon germanium paired with a second conductive metal oxide. The second conductive metal oxide (e.g., aluminum oxide) may be different from the first conductive metal oxide (e.g., titanium oxide).

Abstract: Systems and methods for providing a Barrier Modulated Cell (BMC) structure with reduced shifting in stored memory cell resistance levels over time are described. The BMC structure may comprise a reversible resistance-switching memory element within a memory array comprising a first conductive metal oxide (e.g., titanium oxide) in series with an alternating stack of one or more layers of an amorphous low bandgap material (e.g., germanium) with one or more layers of a second conductive metal oxide (e.g., aluminum oxide). The BMC structure may include a barrier layer comprising a first conductive metal oxide, such as titanium oxide or strontium titanate, in series with a germanium stack that includes a layer of amorphous germanium or amorphous silicon germanium paired with a second conductive metal oxide. The second conductive metal oxide (e.g., aluminum oxide) may be different from the first conductive metal oxide (e.g., titanium oxide).

Abstract: A method is provided that includes forming a word line above a substrate, the word line disposed in a first direction, forming a bit line above the substrate, the bit line disposed in a second direction perpendicular to the first direction, forming a nonvolatile memory material between the word line and the bit line, and forming a memory cell including the nonvolatile memory material at an intersection of the bit line and the word line. The nonvolatile memory material includes a semiconductor material layer, and a conductive oxide material layer including a first conductive oxide material layer portion and a second conductive oxide material layer portion. The method also includes forming a barrier material layer between the first conductive oxide material layer portion and the second conductive oxide material layer portion.

Abstract: A method is provided that includes forming a word line above a substrate, the word line disposed in a first direction, forming a bit line above the substrate, the bit line disposed in a second direction perpendicular to the first direction, forming a nonvolatile memory material between the word line and the bit line, and forming a memory cell including the nonvolatile memory material at an intersection of the bit line and the word line. The word line includes a first portion and a second portion including an electrically conductive carbon-containing material. The nonvolatile memory material includes a semiconductor material layer and a conductive oxide material layer, with the semiconductor material layer disposed adjacent the second portion of the word line.

Abstract: A method is provided that includes forming a word line above a substrate, the word line disposed in a first direction, forming a bit line above the substrate, the bit line disposed in a second direction perpendicular to the first direction, forming a nonvolatile memory material between the word line and the bit line, the nonvolatile memory material including a semiconductor material layer and conductive oxide material layer, forming a first barrier material layer between the word line and the nonvolatile memory material, forming a second barrier material layer between the bit line and the nonvolatile memory material, and forming a memory cell including the nonvolatile memory material at an intersection of the bit line and the word line.

Abstract: A matrix rail structure is formed over a substrate. The matrix rail structure includes a pair of lengthwise sidewalls that extend along a first horizontal direction and comprises, or is at least partially subsequently replaced with, a set of at least one gate electrode rail extending along the first horizontal direction and straight-sidewalled gate dielectrics. A pair of vertical semiconductor channel strips and a pair of laterally-undulating gate dielectrics can be formed on sidewalls of the matrix rail structure for each vertical field effect transistor. At least one laterally-undulating gate electrode extending along the first horizontal direction is formed on the laterally-undulating gate dielectrics. Bottom active regions and top active regions are formed at end portions of the vertical semiconductor channel strips. The vertical field effect transistors can be formed as a two-dimensional array, and may be employed as access transistors for a three-dimensional memory device.

Abstract: A matrix rail structure is formed over a substrate. The matrix rail structure includes a pair of lengthwise sidewalls that extend along a first horizontal direction and comprises, or is at least partially subsequently replaced with, a set of at least one gate electrode rail extending along the first horizontal direction and straight-sidewalled gate dielectrics. A pair of vertical semiconductor channel strips and a pair of laterally-undulating gate dielectrics can be formed on sidewalls of the matrix rail structure for each vertical field effect transistor. At least one laterally-undulating gate electrode extending along the first horizontal direction is formed on the laterally-undulating gate dielectrics. Bottom active regions and top active regions are formed at end portions of the vertical semiconductor channel strips. The vertical field effect transistors can be formed as a two-dimensional array, and may be employed as access transistors for a three-dimensional memory device.

Abstract: A method is provided that includes forming a word line above a substrate, the word line disposed in a first direction, the word line including a first portion including a first conductive material and a second portion including a second conductive material, forming a bit line above the substrate, the bit line disposed in a second direction perpendicular to the first direction, forming a nonvolatile memory material between the word line and the bit line, the nonvolatile memory material including a semiconductor material layer and a conductive oxide material layer, the semiconductor material layer disposed adjacent the second portion of the word line, and forming a memory cell including the nonvolatile memory material at an intersection of the local bit line and the word line.

Abstract: A method is provided that includes providing a memory device including a first word line, a vertical bit line, a non-volatile memory material disposed between the first word line and the vertical bit line, and a memory cell disposed between the first word line and the vertical bit line. The first word line has a first height. The method further includes forming one or more conductive filaments in the memory cell. The one or more conductive filaments are substantially confined to a filament region having a second height less than the first height and disposed substantially about a vertical center of the memory cell.

Abstract: A method is provided that includes providing a memory device including a first word line, a vertical bit line, a non-volatile memory material disposed between the first word line and the vertical bit line, and a memory cell disposed between the first word line and the vertical bit line. The first word line has a first height. The method further includes forming one or more conductive filaments in the memory cell. The one or more conductive filaments are substantially confined to a filament region having a second height less than the first height and disposed substantially about a vertical center of the memory cell.

Abstract: A method is provided that includes forming a vertical bit line disposed in a first direction above a substrate, forming a multi-layer word line disposed in a second direction above the substrate, the second direction perpendicular to the first direction, and forming a memory cell including a nonvolatile memory material at an intersection of the vertical bit line and the multi-layer word line. The multi-layer word line includes a first conductive material layer and a second conductive material layer disposed above the first conductive material layer. The memory cell includes a working cell area encompassed by an intersection of the first conductive material layer and the nonvolatile memory material.