Patents by Inventor Juanita DeLoach
Juanita DeLoach has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8546259Abstract: Semiconductor components are often fabricated that include a nickel silicide layer, e.g., as part of a gate electrode in a transistor component, which may be formed by forming a layer of nickel on a silicon-containing area of the semiconductor substrate, followed by thermally annealing the semiconductor substrate to produce a nickel silicide. However, nickel may tend to diffuse into silicon during the thermal anneal, and may form crystals that undesirably increase the sheet resistance in the transistor. Carbon may be placed with the nickel to serve as a diffusion suppressant and/or to prevent nickel crystal formation during thermal annealing. Methods are disclosed for utilizing this technique, as well as semiconductor components formed in accordance with this technique.Type: GrantFiled: September 26, 2007Date of Patent: October 1, 2013Assignee: Texas Instruments IncorporatedInventors: Juanita DeLoach, Jiong-Ping Lu, Haowen Bu
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Patent number: 7897513Abstract: The present application is directed to a method for forming a metal silicide layer. The method comprises providing a substrate comprising silicon and depositing a metal layer on the substrate. The metal layer is annealed within a first temperature range and for a first dwell time of about 10 milliseconds or less to react at least a portion of the metal with the silicon to form a silicide. An unreacted portion of the metal is removed from the substrate. The silicide is annealed within a second temperature range for a second dwell time of about 10 milliseconds or less.Type: GrantFiled: June 28, 2007Date of Patent: March 1, 2011Assignee: Texas Instruments IncorporatedInventors: Haowen Bu, Shashank Ekbote, Juanita Deloach
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Patent number: 7670952Abstract: A method of manufacturing a semiconductor device, comprising forming a metal silicide gate electrode on a semiconductor substrate surface. The method also comprises exposing the metal silicide gate electrode and the substrate surface to a cleaning process. The cleaning process includes a dry plasma etch using an anhydrous fluoride-containing feed gas and a thermal sublimation configured to leave the metal silicide gate electrode substantially unaltered. The method also comprises depositing a metal layer on source and drain regions of the substrate surface and annealing the metal layer and the source and drain regions of the substrate surface to form metal silicide source and drain contacts.Type: GrantFiled: March 23, 2007Date of Patent: March 2, 2010Assignee: Texas Instruments IncorporatedInventors: Yaw S. Obeng, Juanita DeLoach, Freidoon Mehrad
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Publication number: 20090079010Abstract: Semiconductor components are often fabricated that include a nickel silicide layer, e.g., as part of a gate electrode in a transistor component, which may be formed by forming a layer of nickel on a silicon-containing area of the semiconductor substrate, followed by thermally annealing the semiconductor substrate to produce a nickel silicide. However, nickel may tend to diffuse into silicon during the thermal anneal, and may form crystals that undesirably increase the sheet resistance in the transistor. Carbon may be placed with the nickel to serve as a diffusion suppressant and/or to prevent nickel crystal formation during thermal annealing. Methods are disclosed for utilizing this technique, as well as semiconductor components formed in accordance with this technique.Type: ApplicationFiled: September 26, 2007Publication date: March 26, 2009Inventors: Juanita DeLoach, Jiong-Ping Lu, Haowen Bu
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Publication number: 20090020791Abstract: Exemplary embodiments provide IC CMOS devices having dual stress layers and methods for their manufacture using a buffer layer stack between the two types of the stress layers. The buffer layer stack can include multiple buffer layers formed between a first type stress layer (e.g., a tensile stress layer) and a second type stress layer (e.g., a compressive stress layer) during the CMOS fabrication. Specifically, the buffer layer stack can be formed after the etching process of the first type stress layer but prior to the etching process of the second type stress layer, and thus to protect the etched first type stress layer during the subsequent etching process of the overlaid second type stress layer. In addition, a portion of the buffer layer stack can be formed between, for example, the compressive stress layer and the underlying PMOS device to enhance their adhesion.Type: ApplicationFiled: July 16, 2007Publication date: January 22, 2009Inventors: Shaofeng Yu, Juanita DeLoach, Brian A. Smith, Yaw S. Obeng, Scott Gregory Bushman
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Publication number: 20090004853Abstract: The present application is directed to a method for forming a metal silicide layer. The method comprises providing a substrate comprising silicon and depositing a metal layer on the substrate. The metal layer is annealed within a first temperature range and for a first dwell time of about 10 milliseconds or less to react at least a portion of the metal with the silicon to form a silicide. An unreacted portion of the metal is removed from the substrate. The silicide is annealed within a second temperature range for a second dwell time of about 10 milliseconds or less.Type: ApplicationFiled: June 28, 2007Publication date: January 1, 2009Inventors: Haowen Bu, Shashank Ekbote, Juanita Deloach
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Publication number: 20080230846Abstract: A method of manufacturing a semiconductor device, comprising forming a metal silicide gate electrode on a semiconductor substrate surface. The method also comprises exposing the metal silicide gate electrode and the substrate surface to a cleaning process. The cleaning process includes a dry plasma etch using an anhydrous fluoride-containing feed gas and a thermal sublimation configured to leave the metal silicide gate electrode substantially unaltered. The method also comprises depositing a metal layer on source and drain regions of the substrate surface and annealing the metal layer and the source and drain regions of the substrate surface to form metal silicide source and drain contacts.Type: ApplicationFiled: March 23, 2007Publication date: September 25, 2008Applicant: Texas Instruments IncorporatedInventors: Yaw S. Obeng, Juanita DeLoach, Freidoon Mehrad
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Patent number: 7422967Abstract: The present invention provides a method for manufacturing a semiconductor device. In one embodiment of the present invention, without limitation, the method for manufacturing the semiconductor device includes forming a gate structure (120) over a substrate (110) and forming source/drain regions (190) in the substrate (110) proximate the gate structure (120). The method further includes forming fluorine containing regions (220) in the source/drain regions (190) employing a fluorine containing plasma using a power level of less than about 75 Watts, forming a metal layer (310) over the substrate (110) and fluorine containing regions (220), and reacting the metal layer (310) with the fluorine containing regions (220) to form metal silicide regions (410) in the source/drain regions (190).Type: GrantFiled: May 12, 2005Date of Patent: September 9, 2008Assignee: Texas Instruments IncorporatedInventors: Juanita DeLoach, Lindsey H. Hall, Lance S. Robertson, Jiong-Ping Lu, Donald S. Miles
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Patent number: 7320927Abstract: The present invention provides a process of manufacturing an isolation structure for use in a semiconductor device. The process includes forming an opening in a substrate through a patterned photoresist layer 225 and a hardmask layer 215 located over the substrate 205 with plasma, trimming the photoresist layer 225 with a plasma to create an exposed portion 215a of the hardmask layer 215, removing the exposed portion 215a with a plasma to create a trench guide opening 227, and creating a trench 230 through the trench guide opening 227 with a plasma.Type: GrantFiled: October 20, 2003Date of Patent: January 22, 2008Assignee: Texas Instruments IncorporatedInventors: Juanita DeLoach, Brian A. Smith
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Publication number: 20060258091Abstract: The present invention provides a method for manufacturing a semiconductor device. In one embodiment of the present invention, without limitation, the method for manufacturing the semiconductor device includes forming a gate structure (120) over a substrate (110) and forming source/drain regions (190) in the substrate (110) proximate the gate structure (120). The method further includes forming fluorine containing regions (220) in the source/drain regions (190) employing a fluorine containing plasma using a power level of less than about 75 Watts, forming a metal layer (310) over the substrate (110) and fluorine containing regions (220), and reacting the metal layer (310) with the fluorine containing regions (220) to form metal silicide regions (410) in the source/drain regions (190).Type: ApplicationFiled: May 12, 2005Publication date: November 16, 2006Applicant: Texas Instruments Inc.Inventors: Juanita DeLoach, Lindsey Hall, Lance Robertson, Jiong-Ping Lu, Donald Miles
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Patent number: 6905943Abstract: In one embodiment, a method for forming a semiconductor structure in manufacturing a semiconductor device includes providing a pad layer on a surface of a substrate, providing a nitride layer on the pad layer, and providing a sacrificial oxide layer on the nitride layer. In a first etching step, at least the sacrificial oxide and nitride layers are etched to define opposing substantially vertical surfaces of at least the sacrificial oxide and nitride layers. In a second etching step, the nitride layer is etched such that the opposing substantially vertical surfaces of the nitride layer are recessed from the opposing substantially vertical surfaces of the sacrificial oxide layer, the sacrificial oxide layer substantially preventing the nitride layer from decreasing in thickness as a result of the etching of the nitride layer. In a third etching step, the substrate is etched to form a trench extending into the substrate for purposes of defining one or more isolation regions adjacent the trench.Type: GrantFiled: November 6, 2003Date of Patent: June 14, 2005Assignee: Texas Instruments IncorporatedInventors: Juanita DeLoach, Freidoon Mehrad, Brian M. Trentman, Troy A. Yocum
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Publication number: 20050101101Abstract: In one embodiment, a method for forming a semiconductor structure in manufacturing a semiconductor device includes providing a pad layer on a surface of a substrate, providing a nitride layer on the pad layer, and providing a sacrificial oxide layer on the nitride layer. In a first etching step, at least the sacrificial oxide and nitride layers are etched to define opposing substantially vertical surfaces of at least the sacrificial oxide and nitride layers. In a second etching step, the nitride layer is etched such that the opposing substantially vertical surfaces of the nitride layer are recessed from the opposing substantially vertical surfaces of the sacrificial oxide layer, the sacrificial oxide layer substantially preventing the nitride layer from decreasing in thickness as a result of the etching of the nitride layer. In a third etching step, the substrate is etched to form a trench extending into the substrate for purposes of defining one or more isolation regions adjacent the trench.Type: ApplicationFiled: November 6, 2003Publication date: May 12, 2005Inventors: Juanita DeLoach, Freidoon Mehrad, Brian Trentman, Troy Yocum
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Publication number: 20050085047Abstract: The present invention provides a process of manufacturing an isolation structure for use in a semiconductor device. The process includes forming an opening in a substrate through a patterned photoresist layer 225 and a hardmask layer 215 located over the substrate 205 with plasma, trimming the photoresist layer 225 with a plasma to create an exposed portion 215a of the hardmask layer 215, removing the exposed portion 215a with a plasma to create a trench guide opening 227, and creating a trench 230 through the trench guide opening 227 with a plasma.Type: ApplicationFiled: October 20, 2003Publication date: April 21, 2005Applicant: Texas Instruments IncorporatedInventors: Juanita DeLoach, Brian Smith
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Patent number: 6818526Abstract: A method of fabricating a shallow trench isolation structure includes forming outwardly of a semiconductor layer a first oxide layer. A nitride layer is formed outwardly of the first oxide layer. A second oxide layer is formed outwardly of the nitride layer. A trench is formed through the first oxide layer, the nitride layer, and the second oxide layer and into the semiconductor layer. With the second oxide layer protecting an upper surface of the nitride layer, the nitride layer is etched to form a lateral recessed side boundary of the trench at the nitride layer. The shallow trench isolation layer is formed in the trench.Type: GrantFiled: October 2, 2002Date of Patent: November 16, 2004Assignee: Texas Instruments IncorporatedInventors: Freidoon Mehrad, Zhihao Chen, Juanita Deloach
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Publication number: 20040067620Abstract: A method of fabricating a shallow trench isolation structure includes forming outwardly of a semiconductor layer a first oxide layer. A nitride layer is formed outwardly of the first oxide layer. A second oxide layer is formed outwardly of the nitride layer. A trench is formed through the first oxide layer, the nitride layer, and the second oxide layer and into the semiconductor layer. With the second oxide layer protecting an upper surface of the nitride layer, the nitride layer is etched to form a lateral recessed side boundary of the trench at the nitride layer. The shallow trench isolation layer is formed in the trench.Type: ApplicationFiled: October 2, 2002Publication date: April 8, 2004Inventors: Freidoon Mehrad, Zhihao Chen, Juanita Deloach