Abstract: Semiconductor structures having a nanocrystalline core and corresponding nanocrystalline shell and insulator coating, wherein the semiconductor structure includes an anisotropic nanocrystalline core composed of a first semiconductor material, and an anisotropic nanocrystalline shell composed of a second, different, semiconductor material surrounding the anisotropic nanocrystalline core. The anisotropic nanocrystalline core and the anisotropic nanocrystalline shell form a quantum dot. An insulator layer encapsulates the nanocrystalline shell and anisotropic nanocrystalline core.

Abstract: Semiconductor structures having a nanocrystalline core and corresponding nanocrystalline shell and insulator coating, wherein the semiconductor structure includes an anisotropic nanocrystalline core composed of a first semiconductor material, and an anisotropic nanocrystalline shell composed of a second, different, semiconductor material surrounding the anisotropic nanocrystalline core. The anisotropic nanocrystalline core and the anisotropic nanocrystalline shell form a quantum dot. An insulator layer encapsulates the nanocrystalline shell and anisotropic nanocrystalline core.

Abstract: Semiconductor structures having a nanocrystalline core and corresponding nanocrystalline shell and insulator coating, wherein the semiconductor structure includes an anisotropic nanocrystalline core composed of a first semiconductor material, and an anisotropic nanocrystalline shell composed of a second, different, semiconductor material surrounding the anisotropic nanocrystalline core. The anisotropic nanocrystalline core and the anisotropic nanocrystalline shell form a quantum dot. An insulator layer encapsulates the nanocrystalline shell and anisotropic nanocrystalline core.

Abstract: Semiconductor structures having a nanocrystalline core and corresponding nanocrystalline shell and insulator coating, wherein the semiconductor structure includes an anisotropic nanocrystalline core composed of a first semiconductor material, and an anisotropic nanocrystalline shell composed of a second, different, semiconductor material surrounding the anisotropic nanocrystalline core. The anisotropic nanocrystalline core and the anisotropic nanocrystalline shell form a quantum dot. An insulator layer encapsulates the nanocrystalline shell and anisotropic nanocrystalline core.

Abstract: Composites having semiconductor structures embedded in a matrix are described. In an example, a composite includes a matrix material. A plurality of semiconductor structures is embedded in the matrix material. Each semiconductor structure includes an anisotropic nanocrystalline core composed of a first semiconductor material. Each semiconductor structure also includes a nanocrystalline shell composed of a second, different, semiconductor material at least partially surrounding the anisotropic nanocrystalline core. An insulator layer encapsulates each nanocrystalline shell and anisotropic nanocrystalline core pairing.

Abstract: A method comprises coating a plurality of quantum dots with one or more insulating layers, dispensing the coated quantum dots in a sheet, and installing the coated quantum dots sheet in an light emitting diode (LED) lighting or electronic display device.

Abstract: Semiconductor structures having a nanocrystalline core and corresponding nanocrystalline shell and insulator coating, wherein the semiconductor structure includes an anisotropic nanocrystalline core composed of a first semiconductor material, and an anisotropic nanocrystalline shell composed of a second, different, semiconductor material surrounding the anisotropic nanocrystalline core. The anisotropic nanocrystalline core and the anisotropic nanocrystalline shell form a quantum dot. An insulator layer encapsulates the nanocrystalline shell and anisotropic nanocrystalline core.

Abstract: Semiconductor structures having a nanocrystalline core and corresponding nanocrystalline shell are described. In an example, a semiconductor structure includes an anisotropic nanocrystalline core composed of a first semiconductor material and having an aspect ratio between, but not including, 1.0 and 2.0. The semiconductor structure also includes a nanocrystalline shell composed of a second, different, semiconductor material at least partially surrounding the anisotropic nanocrystalline core.

Abstract: Composites having semiconductor structures embedded in a matrix are described. In an example, a composite includes a matrix material. A plurality of semiconductor structures is embedded in the matrix material. Each semiconductor structure includes an anisotropic nanocrystalline core composed of a first semiconductor material. Each semiconductor structure also includes a nanocrystalline shell composed of a second, different, semiconductor material at least partially surrounding the anisotropic nanocrystalline core. An insulator layer encapsulates each nanocrystalline shell and anisotropic nanocrystalline core pairing.

Abstract: In accordance with some embodiments, logical circuits comprising carbon nanotube field effect transistors are disclosed herein.

Abstract: Composites having semiconductor structures embedded in a matrix are described. In an example, a composite includes a matrix material. A plurality of semiconductor structures is embedded in the matrix material. Each semiconductor structure includes an anisotropic nanocrystalline core composed of a first semiconductor material and having an aspect ratio between, but not including, 1.0 and 2.0. Each semiconductor structure also includes a nanocrystalline shell composed of a second, different, semiconductor material at least partially surrounding the anisotropic nanocrystalline core. An insulator layer encapsulates each nanocrystalline shell and anisotropic nanocrystalline core pairing.

Abstract: Semiconductor structures having a nanocrystalline core and corresponding nanocrystalline shell are described. In an example, a semiconductor structure includes an anisotropic nanocrystalline core composed of a first semiconductor material and having an aspect ratio between, but not including, 1.0 and 2.0. The semiconductor structure also includes a nanocrystalline shell composed of a second, different, semiconductor material at least partially surrounding the anisotropic nanocrystalline core.

Abstract: Semiconductor structures having a nanocrystalline core and corresponding nanocrystalline shell and insulator coating are described. In an example, a semiconductor structure includes an anisotropic nanocrystalline core composed of a first semiconductor material and having an aspect ratio between, but not including, 1.0 and 2.0. The semiconductor structure also includes a nanocrystalline shell composed of a second, different, semiconductor material at least partially surrounding the anisotropic nanocrystalline core. An insulator layer encapsulates the nanocrystalline shell and anisotropic nanocrystalline core.

Abstract: Methods and associated structures of forming a microelectronic device are described. Those methods may comprise forming a channel region on a substrate, wherein the channel region comprises at least one CNT, forming at least one source/drain region adjacent the channel region, and then forming a gate electrode on the channel region, wherein a width of the gate electrode comprises about 50 percent to about 90 percent of a width of the contact region.

Abstract: Methods and associated structures of forming a microelectronic device are described. Those methods may comprise forming a channel region on a substrate, wherein the channel region comprises at least one CNT, forming at least one source/drain region adjacent the channel region, and then forming a gate electrode on the channel region, wherein a width of the gate electrode comprises about 50 percent to about 90 percent of a width of the contact region.

Abstract: In one embodiment of the invention, a fuse element for a one time programmable memory may include carbon nanotubes coupled to a first transistor node and to a second transistor node. The carbon nanotubes may have a first resistance which may be changed upon programming the memory cell with low current levels.

Abstract: In one embodiment of the invention, a fuse element for a one time programmable memory may include carbon nanotubes coupled to a first transistor node and to a second transistor node. The carbon nanotubes may have a first resistance which may be changed upon programming the memory cell with low current levels.

Abstract: An embodiment of the present invention is a technique to pattern features. An array of nanowires is placed at a distance to a resist layer. The array forms a plurality of light emitting diodes (LEDs). The distance corresponds to a near-field region of the light emitted by the LEDs with respect to the resist layer. A control circuit controls the LEDs to emit the light to pattern a feature in the resist layer.

Abstract: Methods and associated structures of forming a microelectronic device are described. Those methods comprise forming a plurality of substantially randomly oriented CNT's on a substrate, and forming at least one source/drain pair, wherein the at least one source/drain pair is coupled to the plurality of substantially randomly oriented CNT's.

Abstract: An embodiment of the present invention is a technique to pattern features. An array of nanowires is placed at a distance to a resist layer. The array forms a plurality of light emitting diodes (LEDs). The distance corresponds to a near-field region of the light emitted by the LEDs with respect to the resist layer. A control circuit controls the LEDs to emit the light to pattern a feature in the resist layer.