Abstract: A system for model-based verification of local design rules comprises a processing unit, a verification database wherein a cell reference graph representing an integrated circuit design as a hierarchical collection of cells is stored, a verification function memory wherein a verification function is stored, a friendly worklayer memory, and an unfriendly worklayer memory. Each cell can include shape models and references to lower-level cells. The processing unit first verifies each cell in the cell reference graph that does not reference any lower-level cells, after which the processing unit verifies each cell for which all lower-level cells referenced have been previously verified. During the verification of a selected cell, the processing unit determines whether models in the selected cell interact with other models in the selected cell or with any lower-level cell. Interacting models are referred to as being "unfriendly," and non-interacting models are referred to as being "friendly.

Abstract: A method and apparatus to enable the size reduction of geometric databases used in the analysis of integrated circuit layouts. The results of design rule analysis on the groups of polygon shapes comprising the integrated circuit layout are stored as either in-group results or override results in a dedicated result register memory. In-group results are design rule analysis results which contain only shapes contained in the group being analyzed. Override results are additional shape models produced when the spatial relationship between the shapes in the group being analyzed and shapes in lower level groups invalidate the results previously obtained for those lower level groups. The data base structure is created using a general purpose computer consisting of a CPU connected to a plurality of memories along a common data bus.