Patents by Inventor Judith M. Rubino
Judith M. Rubino has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7468320Abstract: The idea of the invention is to coat the free surface of patterned Cu conducting lines in on-chip interconnections (BEOL) wiring by a 1-20 nm thick metal layer prior to deposition of the interlevel dielectric. This coating is sufficiently thin so as to obviate the need for additional planarization by polishing, while providing protection against oxidation and surface, or interface, diffusion of Cu which has been identified by the inventors as the leading contributor to metal line failure by electromigration and thermal stress voiding. Also, the metal layer increases the adhesion strength between the Cu and dielectric so as to further increase lifetime and facilitate process yield. The free surface is a direct result of the CMP (chemical mechanical polishing) in a damascene process or in a dry etching process by which Cu wiring is patterned. It is proposed that the metal capping layer be deposited by a selective process onto the Cu to minimize further processing.Type: GrantFiled: July 19, 2005Date of Patent: December 23, 2008Assignee: International Business Machines CorporationInventors: Chao-Kun Hu, Robert Rosenberg, Judith M. Rubino, Carlos J. Sambucetti, Anthony K. Stamper
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Patent number: 7407605Abstract: An aqueous seeding solution of palladium acetate, acetic acid and chloride.Type: GrantFiled: May 22, 2007Date of Patent: August 5, 2008Assignee: International Business Machines CorporationInventors: Darryl D. Restaino, Donald F. Canaperi, Judith M. Rubino, Sean P. E. Smith, Richard O. Henry, James E. Fluegel, Mahadevaiyer Krishnan
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Publication number: 20070284654Abstract: A transistor device and method are disclosed for reducing parasitic resistance and enhancing channel mobility using a metal alloy layer over a conductive region. A transistor device may include a conductive region such as a source, drain and/or gate including at least one first conductive material, and a metal alloy layer disposed on substantially all of a surface of the conductive region, the metal alloy layer including a second conductive material different than the at least one first conductive materials. In one embodiment, the second conductive material includes a cobalt and/or nickel alloy. The metal alloy layer provides a non-epitaxial raised source/drain (and gate) to reduce the parasitic series resistance in, for example, nFETs fabricated on UTSOI. In addition, the metal alloy layer may include a stress to enhance mobility in a channel of the transistor device. The metal alloy layer may be formed using a selective electrochemical metal deposition process such as electroless or electrolytic plating.Type: ApplicationFiled: June 8, 2006Publication date: December 13, 2007Inventors: Judith M. Rubino, James Pan, Dinkar Singh, Jonathan Smith, Anna Topol
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Patent number: 7259025Abstract: A method of forming a ferromagnetic liner on conductive lines of magnetic memory devices and a structure thereof. The ferromagnetic liner increases the flux concentration of current run through the conductive lines, reducing the amount of write current needed to switch magnetic memory cells. The conductive lines are formed in a plate-up method, and the ferromagnetic liner is selectively formed on the plated conductive lines. The ferromagnetic liner may also be formed over conductive lines and a top portion of vias in a peripheral region of the workpiece.Type: GrantFiled: December 22, 2006Date of Patent: August 21, 2007Assignees: Infineon Technologies AG, International Business Machines CorporationInventors: Rainer Leuschner, Michael C. Gaidis, Judith M. Rubino, Lubomyr Taras Romankiw
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Patent number: 7253106Abstract: A method to electrolessly plate a CoWP alloy on copper in a reproducible manner that is effective for a manufacturable process. In the method, a seed layer of palladium (Pd) is deposited on the copper by an aqueous seeding solution of palladium acetate, acetic acid and chloride. Thereafter, a complexing solution is applied to remove any Pd ions which are adsorbed on surfaces other than the copper. Finally, a plating solution of cobalt (Co), tungsten (W) and phosphorous (P) is applied to the copper so as to deposit a layer of CoWP on the Pd seed and copper.Type: GrantFiled: December 22, 2004Date of Patent: August 7, 2007Assignee: International Business Machines CorporationInventors: Darryl D. Restaino, Donald F. Canaperi, Judith M. Rubino, Sean P. E. Smith, Richard O. Henry, James E. Fluegel, Mahadevaiyer Krishnan
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Patent number: 7217655Abstract: A composite material comprising a layer containing copper, and an electrodeposited CoWP film on the copper layer. The CoWP film contains from 11 atom percent to 25 atom percent phosphorus and has a thickness from 5 nm to 200 nm. The invention is also directed to a method of making an interconnect structure comprising: providing a trench or via within a dielectric material, and a conducting metal containing copper within the trench or the via; and forming a CoWP film by electrodeposition on the copper layer. The CoWP film contains from 10 atom percent to 25 atom percent phosphorus and has a thickness from 5 nm to 200 nm. The invention is also directed to a interconnect structure comprising a dielectric layer in contact with a metal layer; an electrodeposited CoWP film on the metal layer, and a copper layer on the CoWP film.Type: GrantFiled: February 2, 2005Date of Patent: May 15, 2007Assignee: International Business Machines CorporationInventors: Cyril Cabral, Jr., Stefanie R. Chiras, Emanuel I. Cooper, Hariklia Deligianni, Andrew J. Kellock, Judith M. Rubino, Roger Y. Tsai
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Patent number: 7193323Abstract: A composite material comprising a layer containing copper, and an electrodeposited CoWP film on the copper layer. The CoWP film contains from 11 atom percent to 25 atom percent phosphorus and has a thickness from 5 nm to 200 nm. The invention is also directed to a method of making an interconnect structure comprising: providing a trench or via within a dielectric material, and a conducting metal containing copper within the trench or the via; and forming a CoWP film by electrodeposition on the copper layer. The CoWP film contains from 10 atom percent to 25 atom percent phosphorus and has a thickness from 5 nm to 200 nm. The invention is also directed to a interconnect structure comprising a dielectric layer in contact with a metal layer; an electrodeposited CoWP film on the metal layer, and a copper layer on the CoWP film.Type: GrantFiled: November 18, 2003Date of Patent: March 20, 2007Assignee: International Business Machines CorporationInventors: Cyril Cabral, Jr., Stefanie R. Chiras, Emanuel Cooper, Hariklia Deligianni, Andrew J. Kellock, Judith M. Rubino, Roger Y. Tsai
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Patent number: 7081680Abstract: An electrical structure including a substrate and an interconnect. The substrate includes an electrically conductive and corrosion resistant metallic layer on a metal layer. The interconnect is electrically coupled to the metallic layer. A top surface of the metallic layer is above a top surface of the substrate and a bottom surface of the metallic layer is in direct mechanical contact with a first portion of a top surface of the metal layer. The metal layer is unalloyed and includes a metal.Type: GrantFiled: May 19, 2004Date of Patent: July 25, 2006Assignee: International Business Machines - CorporationInventors: Daniel C. Edelstein, Anthony K. Stamper, Judith M. Rubino, Carlos J. Sambucetti
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Patent number: 7064064Abstract: An integrated circuit structure is disclosed that has a layer of logical and functional devices and an interconnection layer above the layer of logical and functional devices. The interconnection layer has a substrate, conductive features within the substrate and caps positioned only above the conductive features.Type: GrantFiled: February 16, 2005Date of Patent: June 20, 2006Assignee: International Business Machines CorporationInventors: Shyng-Tsong Chen, Timothy J. Dalton, Kenneth M. Davis, Chao-Kun Hu, Fen F. Jamin, Steffen K. Kaldor, Mahadevaiyer Krishnan, Kaushik Kumar, Michael F. Lofaro, Sandra G. Malhotra, Chandrasekhar Narayan, David L. Rath, Judith M. Rubino, Katherine L. Saenger, Andrew H. Simon, Sean P. E. Smith, Wei-tsu Tseng
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Patent number: 6975032Abstract: An integrated circuit structure is disclosed that has a layer of logical and functional devices and an interconnection layer above the layer of logical and functional devices. The interconnection layer has a substrate, conductive features within the substrate and caps positioned only above the conductive features.Type: GrantFiled: December 16, 2002Date of Patent: December 13, 2005Assignee: International Business Machines CorporationInventors: Shyng-Tsong Chen, Timothy J. Dalton, Kenneth M. Davis, Chao-Kun Hu, Fen F. Jamin, Steffen K. Kaldor, Mahadevaiyer Krishnan, Kaushik Kumar, Michael F. Lofaro, Sandra G. Malhotra, Chandrasekhar Narayan, David L. Rath, Judith M. Rubino, Katherine L. Saenger, Andrew H. Simon, Sean P. E. Smith, Wei-tsu Tseng
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Publication number: 20040234679Abstract: A self-aligned (i.e., spatially selective) process for fabricating a corrosion-resistant conductive pad on a substrate, and an associated structure that includes an interconnect to allow a terminal connection to the conductive pad (e.g., a chip-to-package connection). The conductive pad may include a metal such as copper, aluminum, or tungsten. Examples of a relevant interconnect include a wirebond interconnect and a controlled collapse chip connection (C4) interconnect. The self-aligned process generates a metallic layer on an initially exposed metal layer, wherein the metallic layer is electrically conductive and corrosion resistant. The metallic layer includes an alloy or an unalloyed metal. The metal layer may include copper.Type: ApplicationFiled: May 19, 2004Publication date: November 25, 2004Inventors: Daniel C. Edelstein, Anthony K. Stamper, Judith M. Rubino, Carlos J. Sambucetti
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Patent number: 6779711Abstract: A self-aligned process for fabricating a corrosion-resistant conductive pad on a substrate, and a structure that includes an interconnect to allow a terminal connection to the pad. The process generates a metallic layer on an initially exposed metal layer. The metallic layer is electrically conductive and corrosion resistant. The process includes providing a substrate having a metal layer with an exposed surface, depositing a second metal layer on the exposed surface, annealing the substrate to alloy a portion of the metal layer that includes the exposed surface and a portion of the second metal layer, and removing the unalloyed portion of the second metal layer. An alternative process includes providing a metal layer on the substrate, and electroless plating a corrosion-resistant metal or alloy on the metal layer. The alternative process may additionally include electroless plating a second corrosion-resistant metal on the corrosion-resistant metal or alloy.Type: GrantFiled: June 25, 2002Date of Patent: August 24, 2004Assignee: International Business Machines CorporationInventors: Daniel C. Edelstein, Anthony K. Stamper, Judith M. Rubino, Carlos J. Sambucetti
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Publication number: 20040113279Abstract: An integrated circuit structure is disclosed that has a layer of logical and functional devices and an interconnection layer above the layer of logical and functional devices. The interconnection layer has a substrate, conductive features within the substrate and caps positioned only above the conductive features.Type: ApplicationFiled: December 16, 2002Publication date: June 17, 2004Applicant: International Business Machines CorporationInventors: Shyng-Tsong Chen, Timothy J. Dalton, Kenneth M. Davis, Chao-Kun Hu, Fen F. Jamin, Steffen K. Kaldor, Mahadevaiyer Krishnan, Kaushik Kumar, Michael F. Lofaro, Sandra G. Malhotra, Chandrasekhar Narayan, David L. Rath, Judith M. Rubino, Katherine L. Saenger, Andrew H. Simon, Sean P.E. Smith, Wei-tsu Tseng
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Publication number: 20040087046Abstract: A method for testing integrated circuit chips with probe wires on flat solder bumps and IC chips that are equipped with flat solder bumps are disclosed. In the method, an IC chip that has a multiplicity of bond pads and a multiplicity of flat solder bumps are first provided in which each of the solder bumps has a height less than ½ of its diameter on the multiplicity of bond pads. The probe wires can thus be easily used to contact the increased target area on the solder bumps for establishing electrical connection with a test circuit. The probe can further be conducted easily with all the Z height of the bumps are substantially equal. The height of the solder bumps may be suitably controlled by either a planarization process in which soft solder bumps are compressed by a planar surface, or solder bumps are formed in an in-situ mold by either a MSS or an electroplating process for forming solder bumps in the shape of short cylinders.Type: ApplicationFiled: October 17, 2003Publication date: May 6, 2004Applicant: International Business Machines Corporation.Inventors: Madhav Datta, Peter A. Gruber, Judith M. Rubino, Carlos J. Sambucetti, George F. Walker
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Patent number: 6656750Abstract: A method for testing integrated circuit chips with probe wires on flat solder bumps and IC chips that are equipped with flat solder bumps are disclosed. In the method, an IC chip that has a multiplicity of bond pads and a multiplicity of flat solder bumps are first provided in which each of the solder bumps has a height less than ½ of its diameter on the multiplicity of bond pads. The probe wires can thus be easily used to contact the increased target area on the solder bumps for establishing electrical connection with a test circuit. The probe can further be conducted easily with all the Z height of the bumps are substantially equal. The height of the solder bumps may be suitably controlled by either a planarization process in which soft solder bumps are compressed by a planar surface, or solder bumps are formed in an in-situ mold by either a MSS or an electroplating process for forming solder bumps in the shape of short cylinders.Type: GrantFiled: April 29, 1999Date of Patent: December 2, 2003Assignee: International Business Machines CorporationInventors: Madhav Datta, Peter A. Gruber, Judith M. Rubino, Carlos J. Sambucetti, George F. Walker
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Publication number: 20030072928Abstract: A self-aligned (i.e., spatially selective) process for fabricating a corrosion-resistant conductive pad on a substrate, and an associated structure that includes an interconnect to allow a terminal connection to the conductive pad (e.g., a chip-to-package connection). The conductive pad may include a metal such as copper, aluminum, or tungsten. Examples of a relevant interconnect include a wirebond interconnect and a controlled collapse chip connection (C4) interconnect. The self-aligned process generates a metallic layer on an initially exposed metal layer, wherein the metallic layer is electrically conductive and corrosion resistant. The metallic layer includes an alloy or an unalloyed metal. The metal layer may include copper.Type: ApplicationFiled: June 25, 2002Publication date: April 17, 2003Inventors: Daniel C. Edelstein, Anthony K. Stamper, Judith M. Rubino, Carlos J. Sambucetti
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Patent number: 6503834Abstract: The invention provides a process to increase the reliability of BEOL interconnects. The process comprises forming an array of conductors on a dielectric layer on a wafer substrate, polishing the upper surface so that the surfaces of the conductors are substantially co-planar with the upper surface of the dielectric layer, forming an alloy film on the upper surfaces of the conductors, and brush cleaning the upper surfaces of the conductors and the dielectric layer.Type: GrantFiled: October 3, 2000Date of Patent: January 7, 2003Assignee: International Business Machines Corp.Inventors: Xiaomeng Chen, Mahadevaiyer Krishnan, Judith M. Rubino, Carlos J. Sambucetti, Soon-Cheon Seo, James A. Tornello
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Patent number: 6457234Abstract: A self-aligned (i.e., spatially selective) process for fabricating a corrosion-resistant conductive pad on a substrate, and an associated structure that includes an interconnect to allow a terminal connection to the conductive pad (e.g., a chip-to-package connection). The conductive pad may include a metal such as copper, aluminum, or tungsten. The self-aligned process generates a metallic layer on an initially exposed metal layer, wherein the metallic layer is electrically conductive and corrosion resistant. The process may be accomplished by providing a substrate having a metal layer with an exposed surface, depositing a second metal layer on the exposed surface, annealing the substrate to alloy a portion of the metal layer that includes the exposed surface and a portion of the second metal layer, and removing the unalloyed portion of the second metal layer.Type: GrantFiled: May 14, 1999Date of Patent: October 1, 2002Assignee: International Business Machines CorporationInventors: Daniel C. Edelstein, Judith M. Rubino, Carlos J. Sambucetti, Anthony K. Stamper
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Publication number: 20020081842Abstract: A semiconductor structure, having a semiconductor dielectric material having an opening. A first material lining the opening, the first material comprising MXY, where M is selected from the group consisting of cobalt and nickel, X is selected from the group consisting of tungsten and silicon and Y is selected from the group consisting of phosphorus and boron and a second material filling the lined dielectric material.Type: ApplicationFiled: April 14, 2000Publication date: June 27, 2002Inventors: Carlos J. Sambucetti, Steven H. Boettcher, Peter S. Locke, Judith M. Rubino, Soon-Cheon Seo
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Patent number: 6339024Abstract: A method of manufacturing integrated circuits wherein a conductive structure in a topmost semiconductive layer of an integrated circuit is provided having a thickness greater than or equal to 1.5 &mgr;m. The thickness of the conductive structure is sufficiently great as to effectively protect any layers beneath the topmost semiconductive layer from damage from pressure, such as pressure applied by testing probes. In a preferred embodiment, traditional aluminum TD leveling is discarded in favor of gold deposited upon the thickened conductive layer.Type: GrantFiled: June 28, 2000Date of Patent: January 15, 2002Assignee: International Business Machines CorporationInventors: Kevin S. Petrarca, John E. Heidenreich, III, Judith M. Rubino, Carlos J. Sambucetti, Richard P. Volant, George F. Walker