Patents by Inventor Judith Prybyla

Judith Prybyla has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Process for planarization a semiconductor substrate
    Patent number: 6391798
    Abstract: A process for forming a semiconductor wafer with a flat surface is disclosed. In the process, a bare semiconductor wafer that has been sawed from an ingot is provided. A layer of planarization material is formed on at least one major surface of the semiconductor wafer. The layer of planarization material is placed into contact with a respective object having a flat surface. Pressure is applied to cause the planarization material to flow and impart a planar, surface to the layer of planarization material. The planarization material is then hardened. The flat surface is separated from contact with the respective layer of hardened material. The surface flatness is then transferred into the underlying substrate surface.
    Type: Grant
    Filed: July 27, 2000
    Date of Patent: May 21, 2002
    Assignee: Agere Systems Guardian Corp.
    Inventors: Richard Alden DeFelice, Judith Prybyla