Abstract: System and method for reducing the processing time or latency of floating point arithmetic operations by eliminating the need to complement a negative result produced by a subtraction operation. Each of two numbers is subtracted from the other in simultaneous parallel subtraction operations to produce one answer which is positive and one answer which is negative. The answer which is positive is selected as the result of the operation.

Abstract: A data processing system is described in which the available technology is used to provide high performance. The high performance is achieved by having a four-level pipeline for the central processing system, a simplified instruction set and an interface with the coprocessor unit that has a simple and efficient interface with the normal instruction execution. The apparatus implementing the central processing system is closely connected to the instruction set. A discussion of the implementation of the data processing system is provided.

Abstract: In a data processing system with a central processing unit having a pipelined mode of operation, apparatus and method are disclosed for synchronizing the operation of a coprocessor unit with the remainder of the central processing unit, the remainder of the central processing unit being implemented for pipelined execution of instructions. Because the coprocessor unit performs manipulations of logic signal groups that require a longer time for execution than the manipulation contemplated by the requirements of pipelined instruction execution, the coprocessor unit must be synchronized with an instruction stream adapted to use the rigidly controlled pipelined implementation. In order to synchronize the coprocessor unit with the remainder of the central processing unit, the instructions controlling the operation of the coprocessor unit have two portions.

Abstract: A communications device transfers process data between a data processing system and an external device at high speed. The communications device receives command signals from a user process program in the data processing system and from the external device. The communications device generates physical addresses in the data processing system with respect to which process data is to be transferred, the physical addresses being generated in response to virtual addresses supplied in the commands. The communications device and the external device also each include apparatus for signalling the other that data is being transferred at too rapid a rate to be processed, or that data is temporarily not being transferred, to prevent data being lost and an error being sent to the data processing system.