Abstract: A method of evaluating the feasibility of a CoreSight trace architecture in a SoC before the hardware and/or firmware is available allowing for better die size estimates (IO count and gate count) and package requirement for the design in the early stages of planning.

Abstract: A method of evaluating the feasibility of a CoreSight trace architecture in a SoC before the hardware and/or firmware is available allowing for better die size estimates (IO count and gate count) and package requirement for the design in the early stages of planning.

Abstract: A request transaction ordering method and system includes designing of the Open Core Protocol (OCP) bus to an Advanced extensible Interface (AXI) bus bridge. The general flow of the bridge is to accept a plurality of read and write requests from the OCP bus and convert them to a plurality of AXI read and write requests. Control logic is set for each first in first out policy of push and pop control and for a plurality of handshake signals in OCP and in the AXI. The request ordering part of the bridge performs hazard checking to preserve required order policies for both OCP and AXI bus protocols by using a FIFO (first in first out) policy to hold the outstanding writes, a plurality of comparators, a first in first out policy to hold OCP identities for a plurality of read requests.

Abstract: The present invention provides an endian mapping engine for use with a processing system. In one embodiment, the endian mapping engine includes an identification unit configured to identify sending and receiving endian schemes for data transfers between components of the processing system. Additionally, the endian scheme converter also includes a conversion unit coupled to the identification unit and configured to convert the data transfers between the sending and receiving endian schemes corresponding to an employed endian format. In an alternative embodiment, the endian mapping engine further includes a multiplexing unit coupled to the identification unit and configured to provide multiplexing between endian formats for a given endian scheme.

Abstract: A request transaction ordering method and system includes designing of the Open Core Protocol (OCP) bus to an Advanced extensible Interface (AXI) bus bridge. The general flow of the bridge is to accept a plurality of read and write requests from the OCP bus and convert them to a plurality of AXI read and write requests. Control logic is set for each first in first out policy of push and pop control and for a plurality of handshake signals in OCP and in the AXI. The request ordering part of the bridge performs hazard checking to preserve required order policies for both OCP and AXI bus protocols by using a FIFO (first in first out) policy to hold the outstanding writes, a plurality of comparators, a first in first out policy to hold OCP identities for a plurality of read requests.

Abstract: The present invention is directed to a system and method for heterogeneous multiprocessor reference design. In an aspect of the present invention, a method of designing a multiprocessor integrated circuit may include receiving a specification for an integrated circuit having multiprocessors, the specification having a desired functionality. Functional components are chosen which provide the desired functionality of the received specification. The functional components are implemented in a modular multiprocessor reference design as an example system for the multiprocessor integrated circuit. The implemented functional components of the modular multiprocessor reference design may be suitable for testing software for operation by the multiprocessor integrated circuit. Moreover, the modular multiprocessor reference design enables testing of interaction of functional components for providing the desired functionality of the received specification.

Abstract: A method for structuring hardware description language code characterizes a peripheral design so as to facilitate multiple use of the code with different peripheral design configurations in a chip. The code provides one or more configuration options for the peripheral design in a configuration section of the hardware description language code. The one or more configuration options are differentiated by a configuration variable. The configuration options are selected by initializing a selected peripheral design configuration with the configuration variable, such that the value of the configuration variable determines the selection for that specific instance.

Abstract: A reusable software block is adapted to control multiple instantiations of a peripheral device within a system. A device hardware abstraction layer defines offset values for registers of the peripheral device and a data structure for the peripheral device. A platform hardware abstraction layer defines an address map of the system, and is adapted to initialize each instantiation of the peripheral device via calls to the device hardware abstraction layer.

Abstract: File paths for a plurality of IC design files in a hardware description language are abstracted by parsing description files, or a directory of description file names, to identify file paths to each of the plurality of design files in a first environment. An index is generated correlating each design file and its respective file path. In use, a file path in a second environment of an application is defined for each design file, and the index is applied to the file paths in the second environment to define full file paths for each design file through the first and second environments. The design files are then applied to the application using the full file paths.

Abstract: The present invention is directed to a system and method for heterogeneous multiprocessor reference design. In an aspect of the present invention, a method of designing a multiprocessor integrated circuit may include receiving a specification for an integrated circuit having multiprocessors, the specification having a desired functionality. Functional components are chosen which provide the desired functionality of the received specification. The functional components are implemented in a modular multiprocessor reference design as an example system for the multiprocessor integrated circuit. The implemented functional components of the modular multiprocessor reference design may be suitable for testing software for operation by the multiprocessor integrated circuit. Moreover, the modular multiprocessor reference design enables testing of interaction of functional components for providing the desired functionality of the received specification.