Patents by Inventor Judy L. Hoyt
Judy L. Hoyt has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9269633Abstract: Semiconductor device performance is improved via a gate structure having a tunable effective workfunction and reduced gate depletion effects. According to an example embodiment, the design threshold voltage of a semiconductor device is adjusted in a manner that includes providing a gate having a workfunction that enables operation of the semiconductor device at a selected voltage. The gate is formed having two different conductive materials with different electric workfunctions that both significantly contribute to the overall workfunction of the gate. The relative composition, thickness, and arrangement of each of the two conductive materials is selected to attain a gate electrode workfunction that is different than the workfunctions of each of the two layers and that sets the threshold voltage of the semiconductor device. The adjustability of the effective workfunction of the gate electrode can be applied to a variety of semiconductor devices.Type: GrantFiled: May 23, 2014Date of Patent: February 23, 2016Assignee: The Board of Trustees of the Leland Stanford Junior UniversityInventors: Steven Hung, Judy L. Hoyt, James F. Gibbons
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Publication number: 20140329378Abstract: Semiconductor device performance is improved via a gate structure having a tunable effective workfunction and reduced gate depletion effects. According to an example embodiment, the design threshold voltage of a semiconductor device is adjusted in a manner that includes providing a gate having a workfunction that enables operation of the semiconductor device at a selected voltage. The gate is formed having two different conductive materials with different electric workfunctions that both significantly contribute to the overall workfunction of the gate. The relative composition, thickness, and arrangement of each of the two conductive materials is selected to attain a gate electrode workfunction that is different than the workfunctions of each of the two layers and that sets the threshold voltage of the semiconductor device. The adjustability of the effective workfunction of the gate electrode can be applied to a variety of semiconductor devices.Type: ApplicationFiled: May 23, 2014Publication date: November 6, 2014Applicant: The Board of Trustees of the Leland Stanford Junior UniversityInventors: Steven Hung, Judy L. Hoyt, James F. Gibbons
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Patent number: 7920770Abstract: Structures including optical waveguides disposed over substrates having a chamber or trench defined therein, and methods for formation thereof.Type: GrantFiled: May 1, 2008Date of Patent: April 5, 2011Assignee: Massachusetts Institute of TechnologyInventors: Charles Holzwarth, Jason S. Orcutt, Milos Popovic, Judy L. Hoyt, Rajeev Ram
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Patent number: 7867859Abstract: Semiconductor device performance is improved via a gate structure having a tunable effective workfunction and reduced gate depletion effects. According to an example embodiment, the design threshold voltage of a semiconductor device is adjusted in a manner that includes providing a gate having a workfunction that enables operation of the semiconductor device at a selected voltage. The gate is formed having two different conductive materials with different electric workfunctions that both significantly contribute to the overall workfunction of the gate. The relative composition, thickness, and arrangement of each of the two conductive materials is selected to attain a gate electrode workfunction that is different than the workfunctions of each of the two layers and that sets the threshold voltage of the semiconductor device. The adjustability of the effective workfunction of the gate electrode can be applied to a variety of semiconductor devices.Type: GrantFiled: June 17, 2008Date of Patent: January 11, 2011Assignee: The Board of Trustees of the Leland Stanford Junior UniversityInventors: Steven Hung, Judy L. Hoyt, James F. Gibbons
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Publication number: 20090274418Abstract: Structures including optical waveguides disposed over substrates having a chamber or trench defined therein, and methods for formation thereof.Type: ApplicationFiled: May 1, 2008Publication date: November 5, 2009Applicant: MASSACHUSETTS INSTITUTE OF TECHNOLOGYInventors: Charles Holzwarth, Jason S. Orcutt, Milos Popovic, Judy L. Hoyt, Rajeev Ram
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Publication number: 20090072271Abstract: Disclosed is a method of growing thin and smooth germanium (Ge) on a strained or relaxed silicon (Si) layer comprising the steps of: (a) treating surface of the strained or relaxed Si layer to gaseous precursors of both Si (e.g., silane) and Ge (e.g., germane) for a predetermined short time duration ?t, where 1??t?30 seconds; and (b) depositing a thin Ge film on top of said treated Si layer, wherein said treatment step of (a) reduces growth time and surface roughness of the thin Ge film (e.g., sub-5 nm or sub-20 nm thick) deposited on the Si layer. The treatment step (a) can be conducted at a steady predetermined temperature T, where 450?T?900° C. The predetermined short time duration ?t can be chosen such that less than 10 A of SiGe is deposited.Type: ApplicationFiled: September 18, 2008Publication date: March 19, 2009Inventors: Leonardo Gomez, Meekyung Kim, Judy L. Hoyt
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Patent number: 6921914Abstract: A process for producing monocrystalline semiconductor layers. In an exemplary embodiment, a graded Si1-xGex (x increases from 0 to y) is deposited on a first silicon substrate, followed by deposition of a relaxed Si1-yGey layer, a thin strained Si1-zGez layer and another relaxed Si1-yGey layer. Hydrogen ions are then introduced into the strained SizGez layer. The relaxed Si1-yGey layer is bonded to a second oxidized substrate. An annealing treatment splits the bonded pair at the strained Si layer, such that the second relaxed Si1-yGey layer remains on the second substrate. In another exemplary embodiment, a graded Si1-xGex is deposited on a first silicon substrate, where the Ge concentration x is increased from 0 to 1. Then a relaxed GaAs layer is deposited on the relaxed Ge buffer. As the lattice constant of GaAs is close to that of Ge, GaAs has high quality with limited dislocation defects. Hydrogen ions are introduced into the relaxed GaAs layer at the selected depth.Type: GrantFiled: March 17, 2004Date of Patent: July 26, 2005Assignee: Massachusetts Institute of TechnologyInventors: Zhi-Yuan Cheng, Eugene A. Fitzgerald, Dimitri A. Antoniadis, Judy L. Hoyt
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Publication number: 20040173791Abstract: A process for producing monocrystalline semiconductor layers. In an exemplary embodiment, a graded Si1-xGex (x increases from 0 to y) is deposited on a first silicon substrate, followed by deposition of a relaxed Si1-yGey layer, a thin strained Si1-zGez layer and another relaxed Si1-yGey layer. Hydrogen ions are then introduced into the strained SizGez layer. The relaxed Si1-yGey layer is bonded to a second oxidized substrate. An annealing treatment splits the bonded pair at the strained Si layer, such that the second relaxed Si1-yGey layer remains on the second substrate. In another exemplary embodiment, a graded Si1-xGex is deposited on a first silicon substrate, where the Ge concentration x is increased from 0 to 1. Then a relaxed GaAs layer is deposited on the relaxed Ge buffer. As the lattice constant of GaAs is close to that of Ge, GaAs has high quality with limited dislocation defects. Hydrogen ions are introduced into the relaxed GaAs layer at the selected depth.Type: ApplicationFiled: March 17, 2004Publication date: September 9, 2004Applicant: Massachusetts Institute of TechnologyInventors: Zhi-Yuan Cheng, Eugene A. Fitzgerald, Dimitri A. Antoniadis, Judy L. Hoyt
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Publication number: 20040113211Abstract: Semiconductor device (100) performance is improved via a gate structure (120) having a tunable effective workfunction and reduced gate depletion effects. According to an example embodiment of the present invention, the design threshold voltage of a semiconductor device (100) is adjusted in a manner that includes providing a gate having a workfunction that enables operation of the semiconductor device (100) at a selected voltage. The gate is formed having two different conductive materials (130, 135) with different electric workfunctions that both significantly contribute to the overall workfunction of the gate. The relative composition, thickness, and arrangement of each of the two conductive material is selected to attain a gate electrode workfunction that is different than the workfunctions of each of the two layers and that sets the threshold voltage of the semiconductor device (100). In addition, by selecting the order of the layers, carrier depletion in the gate electrode can be avoided.Type: ApplicationFiled: January 16, 2004Publication date: June 17, 2004Inventors: Steven Hung, Judy L Hoyt, James F Gibbons
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Patent number: 6737670Abstract: A process for producing monocrystalline semiconductor layers. In an exemplary embodiment, a graded Si1−xGex (x increases from 0 to y) is deposited on a first silicon substrate, followed by deposition of a relaxed Si1−yGey layer, a thin strained Si1−zGez layer and another relaxed Si1−yGey layer. Hydrogen ions are then introduced into the strained SizGez layer. The relaxed Si1−yGey layer is bonded to a second oxidized substrate. An annealing treatment splits the bonded pair at the strained Si layer, such that the second relaxed Si1−yGey layer remains on the second substrate. In another exemplary embodiment, a graded Si1−xGex is deposited on a first silicon substrate, where the Ge concentration x is increased from 0 to 1. Then a relaxed GaAs layer is deposited on the relaxed Ge buffer. As the lattice constant of GaAs is close to that of Ge, GaAs has high quality with limited dislocation defects.Type: GrantFiled: March 7, 2003Date of Patent: May 18, 2004Assignee: Massachusetts Institute of TechnologyInventors: Zhi-Yuan Cheng, Eugene A. Fitzgerald, Dimitri A. Antoniadis, Judy L. Hoyt
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Patent number: 6713326Abstract: A process for producing monocrystalline semiconductor layers. In an exemplary embodiment, a graded Si1−xGex (x increases from 0 to y) is deposited on a first silicon substrate, followed by deposition of a relaxed Si1−yGey layer, a thin strained Si1−zGez layer and another relaxed Si1−yGey layer. Hydrogen ions are then introduced into the strained SizGez layer. The relaxed Si1−yGey layer is bonded to a second oxidized substrate. An annealing treatment splits the bonded pair at the strained Si layer, such that the second relaxed Si1−yGey layer remains on the second substrate. In another exemplary embodiment, a graded Si1−xGex is deposited on a first silicon substrate, where the Ge concentration x is increased from 0 to 1. Then a relaxed GaAs layer is deposited on the relaxed Ge buffer. As the lattice constant of GaAs is close to that of Ge, GaAs has high quality with limited dislocation defects.Type: GrantFiled: March 4, 2003Date of Patent: March 30, 2004Assignee: Masachusetts Institute of TechnologyInventors: Zhi-Yuan Cheng, Eugene A. Fitzgerald, Dimitri A. Antoniadis, Judy L. Hoyt
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Publication number: 20030168654Abstract: A process for producing monocrystalline semiconductor layers. In an exemplary embodiment, a graded Si1−xGex (x increases from 0 to y) is deposited on a first silicon substrate, followed by deposition of a relaxed Si1−yGey layer, a thin strained Si1−zGez layer and another relaxed Si1−yGey layer. Hydrogen ions are then introduced into the strained SizGez layer. The relaxed Si1−yGey layer is bonded to a second oxidized substrate. An annealing treatment splits the bonded pair at the strained Si layer, such that the second relaxed Si1−yGey layer remains on the second substrate. In another exemplary embodiment, a graded Si1−xGex is deposited on a first silicon substrate, where the Ge concentration x is increased from 0 to 1. Then a relaxed GaAs layer is deposited on the relaxed Ge buffer. As the lattice constant of GaAs is close to that of Ge, GaAs has high quality with limited dislocation defects.Type: ApplicationFiled: March 7, 2003Publication date: September 11, 2003Applicant: Massachusetts Institute of TechnologyInventors: Zhi-Yuan Cheng, Eugene A. Fitzgerald, Dimitri A. Antoniadis, Judy L. Hoyt
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Publication number: 20030155568Abstract: A process for producing monocrystalline semiconductor layers. In an exemplary embodiment, a graded Si1−xGex (x increases from 0 to y) is deposited on a first silicon substrate, followed by deposition of a relaxed Si1−yGey layer, a thin strained Si1−zGez layer and another relaxed Si1−yGey layer. Hydrogen ions are then introduced into the strained SizGez layer. The relaxed Si1−yGey layer is bonded to a second oxidized substrate. An annealing treatment splits the bonded pair at the strained Si layer, such that the second relaxed Si1−yGey layer remains on the second substrate. In another exemplary embodiment, a graded Si1−xGex is deposited on a first silicon substrate, where the Ge concentration x is increased from 0 to 1. Then a relaxed GaAs layer is deposited on the relaxed Ge buffer. As the lattice constant of GaAs is close to that of Ge, GaAs has high quality with limited dislocation defects.Type: ApplicationFiled: March 4, 2003Publication date: August 21, 2003Applicant: Massachusetts Institute of TechnologyInventors: Zhi-Yuan Cheng, Eugene A. Fitzgerald, Dimitri A. Antoniadis, Judy L. Hoyt
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Patent number: 6573126Abstract: A process for producing monocrystalline semiconductor layers. In an exemplary embodiment, a graded Si1−xGex (x increases from 0 to y) is deposited on a first silicon substrate, followed by deposition of a relaxed Si1−yGey layer, a thin strained Si1−zGez layer and another relaxed Si1−yGey layer. Hydrogen ions are then introduced into the strained SizGez layer. The relaxed Si1−yGey layer is bonded to a second oxidized substrate. An annealing treatment splits the bonded pair at the strained Si layer, such that the second relaxed Si1−yGey layer remains on the second substrate. In another exemplary embodiment, a graded Si1−xGex is deposited on a first silicon substrate, where the Ge concentration x is increased from 0 to 1. Then a relaxed GaAs layer is deposited on the relaxed Ge buffer. As the lattice constant of GaAs is close to that of Ge, GaAs has high quality with limited dislocation defects.Type: GrantFiled: August 10, 2001Date of Patent: June 3, 2003Assignee: Massachusetts Institute of TechnologyInventors: Zhi-Yuan Cheng, Eugene A. Fitzgerald, Dimitri A. Antoniadis, Judy L. Hoyt
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Publication number: 20020072130Abstract: A process for producing monocrystalline semiconductor layers. In an exemplary embodiment, a graded Si1-xGex (x increases from 0 to y) is deposited on a first silicon substrate, followed by deposition of a relaxed Si1-yGey layer, a thin strained Si1-zGez layer and another relaxed Si1-yGey layer. Hydrogen ions are then introduced into the strained SizGz layer. The relaxed Si1-yGey layer is bonded to a second oxidized substrate. An annealing treatment splits the bonded pair at the strained Si layer, such that the second relaxed Si1-yGey layer remains on the second substrate. In another exemplary embodiment, a graded Si1-xGex is deposited on a first silicon substrate, where the Ge concentration x is increased from 0 to 1. Then a relaxed GaAs layer is deposited on the relaxed Ge buffer. As the lattice constant of GaAs is close to that of Ge, GaAs has high quality with limited dislocation defects. Hydrogen ions are introduced into the relaxed GaAs layer at the selected depth.Type: ApplicationFiled: August 10, 2001Publication date: June 13, 2002Inventors: Zhi-Yuan Cheng, Eugene A. Fitzgerald, Dimitri A. Antoniadis, Judy L. Hoyt
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Patent number: 5256550Abstract: The present invention comprises a method of fabricating devices and circuits employing at least one heteroepitaxial layer under strain. The thickness of the heteroepitaxial layer is more than two times the calculated equilibrium critical thickness for an uncapped heteroepitaxial layer upon a crystalline substrate, based on previously known equilibrium theory for the uncapped layer. Subsequent to growth of the heteroepitaxial layer, the structure is processed at temperatures higher than the growth temperature of the heteroepitaxial layer.The strained heteroepitaxial layer (second layer) is epitaxially grown upon the surface of a first, underlaying crystalline layer, creating a heterojunction. Subsequently a third crystalline layer is deposited or grown upon the major exposed surface of the second, strained heteroepitaxial layer. The preferred manner of growth of the third crystalline layer is epitaxial growth.Type: GrantFiled: June 12, 1991Date of Patent: October 26, 1993Assignee: Hewlett-Packard CompanyInventors: Stephen Laderman, Martin Scott, Theodore I. Kamins, Judy L. Hoyt, Clifford A. King, James F. Gibbons, David B. Noble
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Patent number: 5202284Abstract: Several methods are disclosed for minimizing the number of defects or misfit locations in a SiGe layer selectively or non-selectively deposited on a partially oxide masked Si substrate.Type: GrantFiled: December 1, 1989Date of Patent: April 13, 1993Assignee: Hewlett-Packard CompanyInventors: Theodore I. Kamins, David B. Noble, Judy L. Hoyt, James F. Gibbons, Martin P. Scott
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Patent number: 5084411Abstract: Improved devices with silicon to SiGe alloy heterojunctions are provided for in accordance with the following discoveries. X-ray topography and transmission electron microscopy were used to quantify misfit-dislocation spacings in as-grown Si.sub.1-x Ge.sub.x films formed by Limited Reaction Processing (LRP), which is a chemical vapor deposition technique. These analysis techniques were also used to study dislocation formation during annealing of material grown by both LRP and by molecular beam epitaxy (MBE). The thickness at which misfit dislocations first appear in as-grown material was similar for both growth techniques. The thermal stability of capped and uncapped films was also investigated after rapid thermal annealing in the range of 625.degree. to 1000.degree. C. Significantly fewer misfit dislocations were observed in samples containing an epitaxial silicon cap.Type: GrantFiled: November 29, 1988Date of Patent: January 28, 1992Assignee: Hewlett-Packard CompanyInventors: Stephen Laderman, Martin Scott, Theodore I. Kamins, Judy L. Hoyt, Clifford A. King, James F. Gibbons, David B. Noble
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Patent number: 4787551Abstract: Disclosed is a method of welding a temperature-sensing thermocouple to a silicon wafer for sensing the temperature of the wafer during rapid thermal processing using TIG welding and/or electron-beam welding. In one embodiment, a ball of silicon is formed on the bead at one end of a thermocouple by placing the thermocouple on a silicon chip and then melting the silicon chip with a TIG welder. The ball and thermocouple are then placed on the surface of a silicon wafer and the ball and surface are then melted whereby the ball of silicon flows into the silicon wafer. In placing the thermocouple on an edge portion of a silicon wafer, the wafer is supported on a tantalum plate with the edge portion of the wafer extending beyond the plate. A molybdenum sheet is positioned on the top surface of the wafer with the edge portion of the wafer exposed. A TIG arc is established with the molybdenum layer and then the arc is moved to the edge portion of the wafer for melting the silicon.Type: GrantFiled: May 4, 1987Date of Patent: November 29, 1988Assignee: Stanford UniversityInventors: Judy L. Hoyt, Kenneth E. Williams, James F. Gibbons