Patents by Inventor Jue Wu
Jue Wu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11932718Abstract: Exfoliated nanoplatelets functionalized with a non-polar moiety, such as an ethylene or propylene derived polymer, are useful for forming composites, films, and polymer blends.Type: GrantFiled: March 16, 2021Date of Patent: March 19, 2024Assignees: The Texas A&M University System, Formosa Plastics CorporationInventors: Hung-Jue Sue, Joseph Baker, Mingzhen Zhao, Hong-Mao Wu, Wen-Hao Kang, Jen-Long Wu
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Patent number: 11913981Abstract: An electrostatic sensing system configured to sense an electrostatic information of a fluid inside a fluid distribution component and including an electrostatic sensing assembly, a signal amplifier and an analog-to-digital converter. The electrostatic sensing assembly includes a sensing component, and a shield. The sensing component is configured to be disposed at the fluid distribution component. The sensing component is disposed through the fluid distribution component so as to be partially located in the fluid distribution component. The shield surrounds a part of the sensing component that is located in the fluid distribution component. At least part of the shield is located on an upstream side of the sensing component. The signal amplifier is electrically connected to the sensing component. The analog-to-digital converter is electrically connected to the signal amplifier. The shield has an opening spaced apart from the sensing component.Type: GrantFiled: December 21, 2020Date of Patent: February 27, 2024Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Mean-Jue Tung, Ming-Da Yang, Shi-Yuan Tong, Yu-Ting Huang, Chun-Pin Wu
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Publication number: 20240044870Abstract: The present disclosure provides methods, reagents, compositions, systems and kits for high-throughput drug screening by using barcode molecules. In some embodiments, the method uses one step RT-PCR to simplify the experimental procedure and avoid RNA contamination in the experimental process.Type: ApplicationFiled: December 22, 2021Publication date: February 8, 2024Inventors: Kunlun HE, Zhilong JIA, Jue WU, Xinyu SONG, Yu LU, Wenqi ZHU
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Patent number: 11810632Abstract: In various examples, a test system is provided for executing built-in-self-test (BIST) according to JTAG and IEEE 1500 on chips deployed in-field. Hardware and software selectively connect onto the IEEE 1500 serial interface for running BIST while the chip is being used in deployment—such as in an autonomous vehicle. In addition to providing a mechanism to connect onto the serial interface, the hardware and software may reduce memory requirements and runtime associated with running the test sequences, thereby making BIST possible in deployment. Furthermore, some embodiments include components configured to store functional states of clocks, power, and input/output prior to running BIST, which permits restoration of the functional states after the BIST.Type: GrantFiled: August 22, 2022Date of Patent: November 7, 2023Assignee: NVIDIA CorporationInventors: Anitha Kalva, Jue Wu
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Patent number: 11768241Abstract: In various examples, a test system is provided for executing built-in-self-test (BIST) on integrated circuits deployed in the field. The integrated circuits may include a first device and a second device, the first device having direct access to external memory, which stores test data, and the second device having indirect access to the external memory by way of the first device. In addition to providing a mechanism to permit the first device and the second device to run test concurrently, the hardware and software may reduce memory requirements and runtime associated with running the test sequences, thereby making real-time BIST possible in deployment. Furthermore, some embodiments permit a single external memory image to cater to different SKU configurations.Type: GrantFiled: December 20, 2022Date of Patent: September 26, 2023Assignee: NVIDIA CorporationInventors: Anitha Kalva, Jue Wu
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Publication number: 20230273873Abstract: In various examples, a diagnostic circuit is connected to a target system to automatically trigger the target system to enter a diagnostic mode. The diagnostic circuit receives diagnostic data from the target system when the target system performs a diagnostic operation in the diagnostic mode.Type: ApplicationFiled: February 28, 2022Publication date: August 31, 2023Inventors: Padmanabham Patki, Jue Wu, Chung-Hong Lai, Laurent Dahan, Marc Delvaux, Chiang Hsu
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Patent number: 11669421Abstract: Unavoidable physical phenomena, such as an alpha particle strikes, can cause soft errors in integrated circuits. Materials that emit alpha particles are ubiquitous, and higher energy cosmic particles penetrate the atmosphere and also cause soft errors. Some soft errors have no consequence, but others can cause an integrated circuit to malfunction. In some applications (e.g. driverless cars), proper operation of integrated circuits is critical to human life and safety. To minimize or eliminate the likelihood of a soft error becoming a serious malfunction, detailed assessment of individual potential soft errors and subsequent processor behavior is necessary. Embodiments of the present disclosure facilitate emulating a plurality of different, specific soft errors. Resilience may be assessed over the plurality of soft errors and application code may be advantageously engineered to improve resilience.Type: GrantFiled: February 2, 2022Date of Patent: June 6, 2023Assignee: NVIDIA CorporationInventors: Jonah M. Alben, Sachin Satish Idgunji, Jue Wu
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Publication number: 20230143807Abstract: In various examples, a test system is provided for executing built-in-self-test (BIST) on integrated circuits deployed in the field. The integrated circuits may include a first device and a second device, the first device having direct access to external memory, which stores test data, and the second device having indirect access to the external memory by way of the first device. In addition to providing a mechanism to permit the first device and the second device to run test concurrently, the hardware and software may reduce memory requirements and runtime associated with running the test sequences, thereby making real-time BIST possible in deployment. Furthermore, some embodiments permit a single external memory image to cater to different SKU configurations.Type: ApplicationFiled: December 20, 2022Publication date: May 11, 2023Inventors: Anitha Kalva, Jue Wu
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Publication number: 20230123956Abstract: In various examples, one or more components or regions of a processing unit—such as a processing core, and/or component thereof—may be tested for faults during deployment in the field. To perform testing while in deployment, the state of a component subject to test may be retrieved and/or stored during the test to maintain state integrity, the component may be clamped to communicatively isolate the component from other components of the processing unit, a test vector may be applied to the component, and the output of the component may be compared against an expected output to determine if any faults are present. The state of the component may be restored after testing, and the clamp removed, thereby returning the component to its operating state without a perceivable detriment to operation of the processing unit in deployment.Type: ApplicationFiled: December 20, 2022Publication date: April 20, 2023Inventors: Jonah Alben, Sachin Idgunji, Jue Wu, Shantanu Sarangi
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Patent number: 11573872Abstract: In various examples, one or more components or regions of a processing unit—such as a processing core, and/or component thereof—may be tested for faults during deployment in the field. To perform testing while in deployment, the state of a component subject to test may be retrieved and/or stored during the test to maintain state integrity, the component may be clamped to communicatively isolate the component from other components of the processing unit, a test vector may be applied to the component, and the output of the component may be compared against an expected output to determine if any faults are present. The state of the component may be restored after testing, and the clamp removed, thereby returning the component to its operating state without a perceivable detriment to operation of the processing unit in deployment.Type: GrantFiled: December 20, 2021Date of Patent: February 7, 2023Assignee: NVIDIA CorporationInventors: Jonah Alben, Sachin Idgunji, Jue Wu, Shantanu Sarangi
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Patent number: 11573269Abstract: In various examples, a test system is provided for executing built-in-self-test (BIST) on integrated circuits deployed in the field. The integrated circuits may include a first device and a second device, the first device having direct access to external memory, which stores test data, and the second device having indirect access to the external memory by way of the first device. In addition to providing a mechanism to permit the first device and the second device to run test concurrently, the hardware and software may reduce memory requirements and runtime associated with running the test sequences, thereby making real-time BIST possible in deployment. Furthermore, some embodiments permit a single external memory image to cater to different SKU configurations.Type: GrantFiled: July 15, 2021Date of Patent: February 7, 2023Assignee: NVIDIA CorporationInventors: Anitha Kalva, Jue Wu
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Publication number: 20220399069Abstract: In various examples, a test system is provided for executing built-in-self-test (BIST) according to JTAG and IEEE 1500 on chips deployed in-field. Hardware and software selectively connect onto the IEEE 1500 serial interface for running BIST while the chip is being used in deployment—such as in an autonomous vehicle. In addition to providing a mechanism to connect onto the serial interface, the hardware and software may reduce memory requirements and runtime associated with running the test sequences, thereby making BIST possible in deployment. Furthermore, some embodiments include components configured to store functional states of clocks, power, and input/output prior to running BIST, which permits restoration of the functional states after the BIST.Type: ApplicationFiled: August 22, 2022Publication date: December 15, 2022Inventors: Anitha Kalva, Jue Wu
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Patent number: 11424000Abstract: In various examples, a test system is provided for executing built-in-self-test (BIST) according to JTAG and IEEE 1500 on chips deployed in-field. Hardware and software selectively connect onto the IEEE 1500 serial interface for running BIST while the chip is being used in deployment—such as in an autonomous vehicle. In addition to providing a mechanism to connect onto the serial interface, the hardware and software may reduce memory requirements and runtime associated with running the test sequences, thereby making BIST possible in deployment. Furthermore, some embodiments include components configured to store functional states of clocks, power, and input/output prior to running BIST, which permits restoration of the functional states after the BIST.Type: GrantFiled: December 24, 2020Date of Patent: August 23, 2022Assignee: NVIDIA CORPORATIONInventors: Anitha Kalva, Jue Wu
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Publication number: 20220156169Abstract: Unavoidable physical phenomena, such as an alpha particle strikes, can cause soft errors in integrated circuits. Materials that emit alpha particles are ubiquitous, and higher energy cosmic particles penetrate the atmosphere and also cause soft errors. Some soft errors have no consequence, but others can cause an integrated circuit to malfunction. In some applications (e.g. driverless cars), proper operation of integrated circuits is critical to human life and safety. To minimize or eliminate the likelihood of a soft error becoming a serious malfunction, detailed assessment of individual potential soft errors and subsequent processor behavior is necessary. Embodiments of the present disclosure facilitate emulating a plurality of different, specific soft errors. Resilience may be assessed over the plurality of soft errors and application code may be advantageously engineered to improve resilience.Type: ApplicationFiled: February 2, 2022Publication date: May 19, 2022Inventors: Jonah M. Alben, Sachin Satish Idgunji, Jue Wu
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Publication number: 20220114069Abstract: In various examples, one or more components or regions of a processing unit—such as a processing core, and/or component thereof—may be tested for faults during deployment in the field. To perform testing while in deployment, the state of a component subject to test may be retrieved and/or stored during the test to maintain state integrity, the component may be clamped to communicatively isolate the component from other components of the processing unit, a test vector may be applied to the component, and the output of the component may be compared against an expected output to determine if any faults are present. The state of the component may be restored after testing, and the clamp removed, thereby returning the component to its operating state without a perceivable detriment to operation of the processing unit in deployment.Type: ApplicationFiled: December 20, 2021Publication date: April 14, 2022Inventors: Jonah ALBEN, Sachin Idgunji, Jue Wu, Shantanu Sarangi
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Patent number: 11275662Abstract: Unavoidable physical phenomena, such as an alpha particle strikes, can cause soft errors in integrated circuits. Materials that emit alpha particles are ubiquitous, and higher energy cosmic particles penetrate the atmosphere and also cause soft errors. Some soft errors have no consequence, but others can cause an integrated circuit to malfunction. In some applications (e.g. driverless cars), proper operation of integrated circuits is critical to human life and safety. To minimize or eliminate the likelihood of a soft error becoming a serious malfunction, detailed assessment of individual potential soft errors and subsequent processor behavior is necessary. Embodiments of the present disclosure facilitate emulating a plurality of different, specific soft errors. Resilience may be assessed over the plurality of soft errors and application code may be advantageously engineered to improve resilience.Type: GrantFiled: January 7, 2021Date of Patent: March 15, 2022Assignee: NVIDIA CorporationInventors: Jonah M. Alben, Sachin Satish Idgunji, Jue Wu
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Patent number: 11204849Abstract: In various examples, one or more components or regions of a processing unit—such as a processing core, and/or component thereof—may be tested for faults during deployment in the field. To perform testing while in deployment, the state of a component subject to test may be retrieved and/or stored during the test to maintain state integrity, the component may be clamped to communicatively isolate the component from other components of the processing unit, a test vector may be applied to the component, and the output of the component may be compared against an expected output to determine if any faults are present. The state of the component may be restored after testing, and the clamp removed, thereby returning the component to its operating state without a perceivable detriment to operation of the processing unit in deployment.Type: GrantFiled: March 13, 2020Date of Patent: December 21, 2021Assignee: NVIDIA CorporationInventors: Jonah Alben, Sachin Idgunji, Jue Wu, Shantanu Sarangi
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Publication number: 20210341537Abstract: In various examples, a test system is provided for executing built-in-self-test (BIST) on integrated circuits deployed in the field. The integrated circuits may include a first device and a second device, the first device having direct access to external memory, which stores test data, and the second device having indirect access to the external memory by way of the first device. In addition to providing a mechanism to permit the first device and the second device to run test concurrently, the hardware and software may reduce memory requirements and runtime associated with running the test sequences, thereby making real-time BIST possible in deployment. Furthermore, some embodiments permit a single external memory image to cater to different SKU configurations.Type: ApplicationFiled: July 15, 2021Publication date: November 4, 2021Inventors: Anitha Kalva, Jue Wu
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Publication number: 20210286693Abstract: In various examples, one or more components or regions of a processing unit—such as a processing core, and/or component thereof—may be tested for faults during deployment in the field. To perform testing while in deployment, the state of a component subject to test may be retrieved and/or stored during the test to maintain state integrity, the component may be clamped to communicatively isolate the component from other components of the processing unit, a test vector may be applied to the component, and the output of the component may be compared against an expected output to determine if any faults are present. The state of the component may be restored after testing, and the clamp removed, thereby returning the component to its operating state without a perceivable detriment to operation of the processing unit in deployment.Type: ApplicationFiled: March 13, 2020Publication date: September 16, 2021Inventors: Jonah ALBEN, Sachin Idgunji, Jue Wu, Shantanu Sarangi
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Patent number: 11079434Abstract: In various examples, a test system is provided for executing built-in-self-test (BIST) on integrated circuits deployed in the field. The integrated circuits may include a first device and a second device, the first device having direct access to external memory, which stores test data, and the second device having indirect access to the external memory by way of the first device. In addition to providing a mechanism to permit the first device and the second device to run test concurrently, the hardware and software may reduce memory requirements and runtime associated with running the test sequences, thereby making real-time BIST possible in deployment. Furthermore, some embodiments permit a single external memory image to cater to different SKU configurations.Type: GrantFiled: October 10, 2019Date of Patent: August 3, 2021Assignee: NVIDIA CorporationInventors: Anitha Kalva, Jue Wu