Abstract: A display panel is provided. At least two first wires in a second direction are electrically connected to each other and at least two second wires in the second direction are electrically connected to each other. The space in the second direction is fully used to arrange the first wires and the second wires to ensure the number of first via holes disposed corresponding to the first wires and the number of second via holes disposed corresponding to the second wire, thereby ensuring the connectivity of a transparent conductive block that bridges the first wires and the second wires through the first via holes and the second via holes.

Abstract: A display panel of the present application is disclosed. The display panel includes a GOA circuit, a plurality of clock main lines on a side of the GOA circuit, and a plurality of clock branch lines connected to each of the corresponding clock main lines, respectively. By providing the different first protrusion components and second protrusion components in the corresponding clock branch lines, the equivalent impedance of these clock branch lines can be adjusted to be equal. By providing the bridge components with different areas in the corresponding clock branch lines, the equivalent capacitive reactance of these clock branch lines can be adjusted to be equal.

Abstract: A display panel is provided. At least two first wires in a second direction are electrically connected to each other and at least two second wires in the second direction are electrically connected to each other. The space in the second direction is fully used to arrange the first wires and the second wires to ensure the number of first via holes disposed corresponding to the first wires and the number of second via holes disposed corresponding to the second wire, thereby ensuring the connectivity of a transparent conductive block that bridges the first wires and the second wires through the first via holes and the second via holes.

Abstract: A gate drive circuit and a display panel are provided. The gate drive circuit includes N clock signal lines and a plurality of gate drive units. Each of the gate drive units is connected to at least one of the clock signal lines. Each of the clock signal lines is provided with a capacitance compensation unit, a sum of an area of any one of the clock signal lines and an area of the capacitance compensation unit provided on the same clock signal line is equal to a predetermined area, and N is an integer greater than or equal to 2.

Abstract: A gate drive circuit and a display panel are provided. The gate drive circuit includes N clock signal lines and a plurality of gate drive units. Each of the gate drive units is connected to at least one of the clock signal lines. Each of the clock signal lines is provided with a capacitance compensation unit, a sum of an area of any one of the clock signal lines and an area of the capacitance compensation unit provided on the same clock signal line is equal to a predetermined area, and N is an integer greater than or equal to 2.