Abstract: A successive approximation register analog-to-digital converter including separable dual capacitor array is disclosed. The disclosed successive approximation register analog-to-digital converter comprises: a dual capacitor array configured to include a first capacitor array for converting most significant bits of n bits and a second capacitor array for converting least significant bits of the n bits; a comparator configured to compare a level signal outputted from the first capacitor array with a level signal outputted from the second capacitor array; and an SAR logic circuit configured to convert an analog input voltage into a digital signal having the n bits by using the comparison result. Here, the first capacitor array includes a 1-1 capacitor circuit and a 1-2 capacitor circuit and the second capacitor array includes a 2-1 capacitor circuit and a 2-2 capacitor circuit. Each of the capacitor circuits includes capacitors connected in parallel each other.

Abstract: An asynchronous successive approximation register analog-to-digital converter and an internal clock generator included in the same are disclosed. The internal clock generator in an SAR ADC comprises a detection unit configured to generate an up pulse or a down pulse by sensing generation time of a final internal clock and next external clock; and a delay block configured to increase or decrease delay time by controlling a bias voltage according to the generated up pulse or the generated down pulse.

Abstract: An asynchronous successive approximation register analog-to-digital converter and an internal clock generator included in the same are disclosed. The internal clock generator in an SAR ADC comprises a detection unit configured to generate an up pulse or a down pulse by sensing generation time of a final internal clock and next external clock; and a delay block configured to increase or decrease delay time by controlling a bias voltage according to the generated up pulse or the generated down pulse.

Abstract: A successive approximation register analog-to-digital converter including separable dual capacitor array is disclosed. The disclosed successive approximation register analog-to-digital converter comprises: a dual capacitor array configured to include a first capacitor array for converting most significant hits of n bits and a second capacitor array for converting least significant bits of the n bits; a comparator configured to compare a level signal outputted from the first capacitor array with a level signal outputted from the second capacitor array; and an SAR logic circuit configured to convert an analog input voltage into a digital signal having the n bits by using the comparison result. Here, the first capacitor array includes a 1-1 capacitor circuit and a 1-2 capacitor circuit and the second capacitor array includes a 2-1 capacitor circuit and a 2-2 capacitor circuit. Each of the capacitor circuits includes capacitors connected in parallel each other.