Abstract: In a general aspect, an apparatus can include an insulated-gate bipolar transistor device (IGBT), a gate driver circuit (driver) coupled with a gate terminal of the IGBT and a low-resistance switch device coupled between an emitter terminal of the IGBT and an electrical ground terminal, the low-resistance switch device being coupled with the electrical ground terminal via a resistor. The apparatus can also include a current sensing circuit coupled with the driver and a current sense signal line coupled with the current sensing circuit and a current sense node, the current sense node being disposed between the low-resistance switch device and the resistor. The apparatus can further include a control circuit configured, when the driver is off, to detect, based on a voltage on the current sense node, when a current through the resistor is above a threshold value and disable the IGBT in response to the detection.

Abstract: Devices and methods provide a protection device for maintaining a steady output on a gate driver terminal despite fluctuations in a power supply, the protection device including low voltage detection circuitry configured to monitor the power supply and detect fluctuations in the power supply; and gate isolation circuitry configured to isolate the gate driver terminal from the power supply if the low voltage detection circuitry detects a fluctuation in the power supply, wherein a voltage of the gate driver terminal is maintained within a preselected range when the gate is isolated.

Abstract: In a general aspect, an apparatus can include an insulated-gate bipolar transistor device (IGBT), a gate driver circuit (driver) coupled with a gate terminal of the IGBT and a low-resistance switch device coupled between an emitter terminal of the IGBT and an electrical ground terminal, the low-resistance switch device being coupled with the electrical ground terminal via a resistor. The apparatus can also include a current sensing circuit coupled with the driver and a current sense signal line coupled with the current sensing circuit and a current sense node, the current sense node being disposed between the low-resistance switch device and the resistor. The apparatus can further include a control circuit configured, when the driver is off, to detect, based on a voltage on the current sense node, when a current through the resistor is above a threshold value and disable the IGBT in response to the detection.

Abstract: Devices and methods provide a protection device for maintaining a steady output on a gate driver terminal despite fluctuations in a power supply, the protection device including low voltage detection circuitry configured to monitor the power supply and detect fluctuations in the power supply; and gate isolation circuitry configured to isolate the gate driver terminal from the power supply if the low voltage detection circuitry detects a fluctuation in the power supply, wherein a voltage of the gate driver terminal is maintained within a preselected range when the gate is isolated.

Abstract: Techniques that may aid in the recovery of clock and data signals include receiving a stream of incoming data signals and determining an offset based, at least in part, on the state of a transition bit sampled from the stream of incoming data signals. The slice level of an input sampling circuit is adjusted based on the offset. Re-timed data signals corresponding to the incoming data signals may be generated.

Abstract: Techniques that may aid in the recovery of clock and data signals include receiving a stream of incoming data signals and determining an offset based, at least in part, on the state of a transition bit sampled from the stream of incoming data signals. The slice level of an input sampling circuit is adjusted based on the offset. Re-timed data signals corresponding to the incoming data signals may be generated.

Abstract: A method and apparatus is disclosed for generating, based upon user input, clock signals which are delayed by sub-delays which are of a size that is smaller than the smallest achievable delay of a conventional delay element. A user can selectively add one or more sub-delays by providing control inputs which define the desired number of sub-delays to be added.

Abstract: A integrated circuit buffer includes a first inverter comprising a pull-up transistor of a first conductivity type (e.g., p-channel) and a pull-down transistor of a second conductivity type (e.g., n-channel) for driving a load. The buffer further includes a second inverter comprising a pull-up transistor of the second conductivity type (e.g., n-channel) and a pull-down transistor of the first conductivity type (e.g., p-channel) that also drives the load. The first and second inverters are driven by a drive circuit that provides signals that are substantially out of phase. Therefore, in operation the pull-up transistors are active during a first time period, and the pull-down transistors are active during a second time period. In this manner, the drive capability of the buffer is improved in the face of voltage bounce on the power supply bondpads, which is typically due to package inductance.

Abstract: A particular electrostatic discharge (ESD) protection problem is faced when only n-channel output transistors are present, since there is no p-n junction that could serve to clamp positive ESD voltages, as would be the case if a p-channel output transistor were present. In the present technique, a capacitor couples a bond pad to the gate of a protective transistor that applies a turn-on voltage to the gate of an n-channel output transistor. In this manner, the output transistor itself is used to conduct the ESD current to a power supply conductor (V.sub.SS). In one embodiment, to assist in the turn-on of the n-channel output transistor, a transistor couples the bond pad to the n-tub in which the p-channel pre-driver transistor is formed. Conduction through this transistor raises the n-tub voltage when an ESD event occurs, thereby preventing the p-n junction of the p-channel driver transistor from clamping the turn-on voltage, which would limit the protection obtained by this technique.

Abstract: A particular electrostatic discharge (ESD) protection problem is faced when only n-channel output transistors are present, since there is no p-n junction that could serve to clamp positive ESD voltages, as would be the case if a p-channel output transistor were present. In the present technique, the output transistor itself is used to conduct the ESD current to a power supply conductor (V.sub.SS). To assist in the turn-on of the n-channel output transistor, a transistor couples the bond pad to the n-tub in which the p-channel pre-driver transistor is formed. Conduction through this transistor raises the n-tub voltage when an ESD event occurs, thereby preventing the p-n junction of the p-channel pre-driver transistor from clamping the turn-on voltage, which would limit the protection obtained by this technique. This technique is especially valuable for SCSI (Small Computer System Interface) chips, since only n-channel output transistors are used.