Abstract: A quantum computing system having a central controller with improved latency executes a first instruction at a processing unit of the central controller. The central controller interconnects a plurality of control entities for configuring and measuring a plurality of qubits. A set of selected channels carry measurement results for a first quantum computation by the plurality of qubits. When the first instruction is a multi-channel-receive instruction, the system stalls the processing unit from executing any further instructions until each channel of the set of two or more selected channels has provided an input from a remote peer. Different channels in the set of selected channels are examined simultaneously. The system resumes execution at the processing unit of a second instruction after the stalling.

Abstract: A quantum computing system that supports efficient multitasking receives messages from a classical computing system to a pool of qubits. Each received message is associated with a partition identifier. The system configures a first set of qubits in the pool of qubits to perform a first computing task based on received messages that are associated with a first partition identifier and a second set of qubits in the pool of qubits to perform a second computing task based on received messages that are associated with a second partition identifier. The system acquires a first set of measurements from the first set of qubits and a second set of measurements from the second set of qubits. The system relays the first and second sets of measurements to the classical computing system.

Abstract: Embodiments are provided for centralized control of execution of a quantum program. In some embodiments, a system can include a processor that executes computer-executable components stored in memory. The computer-executable components include a synchronization component that causes multiple controller devices remotely located relative to the system to be synchronized with one another and the system. The computer-executable components also include an ingestion component that accesses measurement data resulting from one or more measurements at respective qubit devices. The computer-executable components further include a composition component that generates, using the measurement data, one or more control messages for respective second controller devices of the multiple controller devices.

Abstract: Embodiments are provided for centralized control of execution of a quantum program. In some embodiments, a system can include a processor that executes computer-executable components stored in memory. The computer-executable components include a synchronization component that causes multiple controller devices remotely located relative to the system to be synchronized with one another and the system. The computer-executable components also include an ingestion component that accesses measurement data resulting from one or more measurements at respective qubit devices. The computer-executable components further include a composition component that generates, using the measurement data, one or more control messages for respective second controller devices of the multiple controller devices.

Abstract: A method for determining current return path integrity in an electric device with a plurality of signal lines and supply lines. A library with at least one reference signal pattern of a near end crosstalk signal on a defined signal line arising from an input signal on another defined signal line is provided, a predetermined signal to a selected signal line of the electric device is applied, the near end crosstalk signal on at least one further signal line of the electric device is detected, said near end crosstalk signal is compared with the corresponding reference signal pattern from the library, and if there is a deviation between the near end crosstalk signal and the corresponding reference signal pattern, an information that there is any defect in the electric device is displayed.

Abstract: A method for determining current return path integrity in an electric device with a plurality of signal lines and supply lines. A library with at least one reference signal pattern of a near end crosstalk signal on a defined signal line arising from an input signal on another defined signal line is provided, a predetermined signal to a selected signal line of the electric device is applied, the near end crosstalk signal on at least one further signal line of the electric device is detected, said near end crosstalk signal is compared with the corresponding reference signal pattern from the library, and if there is a deviation between the near end crosstalk signal and the corresponding reference signal pattern, an information that there is any defect in the electric device is displayed.

Abstract: The present invention relates to a method for validating the correct logical function and timing behavior of a digital circuit design within a cycle-based verification environment. The method comprises the steps of providing a VHDL description of the digital circuit design, performing a logic synthesis, wherein the VHDL description is turned into a design implementation in terms of logic gates, and creating a netlist including the elements of the digital circuit design and the connections between said elements. The method comprises the further steps of providing a transformation script with at least one transparent storage element, wherein said transparent storage element represents a path delay within the digital circuit design, creating a new netlist with the at least one transparent storage elements, running a verification, and checking if the new netlist is clean from a logical and timing point of view.

Abstract: A method and corresponding apparatus is provided for determining the location of a configuration server being connected to a totally symmetric network infrastructure that does not exhibit any symmetry breakers on network level. The configuration server reaches a decision to determine its network-wide unique configuration in order to be able to serve controllers. This decision depends on the plug position of the configuration server under consideration and the assumption of plugging rules governing a “good” network infrastructure. The controllers periodically send network packets that will be marked if they traverse specific connection elements in the network. The origin and the path of a network packet can be determined. The decision making is based on a majority function based on the packets received by the configuration server. If a decision cannot be made, then errors in the cabling structure can be detected.

Abstract: A cascaded interconnect system for providing a service interface to a memory system. The cascaded interconnect system includes a master service interface module, a service interface bus, and one or more slave service interface modules. The master service interface module and the slave interface modules are cascade interconnected via the service interface bus. Each slave service interface module is in communication with a corresponding memory module for providing a service to the memory module.

Abstract: The present invention relates to a method for validating the correct logical function and timing behavior of a digital circuit design within a cycle-based verification environment. Said method comprises the steps of providing (10) a VHDL description of the digital circuit design, performing (12) a logic synthesis, wherein the VHDL description is turned into a design implementation in terms of logic gates, and creating (14) a netlist including the elements of the digital circuit design and the connections between said elements. Said method comprises the further steps of providing (28) a transformation script with at least one transparent storage element (40; 54), wherein said transparent storage element (40; 54) represents a path delay within the digital circuit design, creating (30) a new netlist with the at least one transparent storage elements (40; 54), running (20) a verification, and checking, if the new netlist is clean from a logical and timing point of view.

Abstract: A method and corresponding apparatus is provided for determining the location of a configuration server being connected to a totally symmetric network infrastructure that does not exhibit any symmetry breakers on network level. The configuration server reaches a decision to determine its network-wide unique configuration in order to be able to serve controllers. This decision depends on the plug position of the configuration server under consideration and the assumption of plugging rules governing a “good” network infrastructure. The controllers periodically send network packets that will be marked if they traverse specific connection elements in the network. The origin and the path of a network packet can be determined. The decision making is based on a majority function based on the packets received by the configuration server. If a decision cannot be made, then errors in the cabling structure can be detected.

Abstract: A cascaded interconnect system for providing a service interface to a memory system. The cascaded interconnect system includes a master service interface module, a service interface bus, and one or more slave service interface modules. The master service interface module and the slave interface modules are cascade interconnected via the service interface bus. Each slave service interface module is in communication with a corresponding memory module for providing a service to the memory module.

Abstract: A cascaded interconnect system for providing a service interface to a memory system. The cascaded interconnect system includes a master service interface module, a service interface bus, and one or more slave service interface modules. The master service interface module and the slave interface modules are cascade interconnected via the service interface bus. Each slave service interface module is in communication with a corresponding memory module for providing a service to the memory module.

Abstract: A system and method for an initial boot of a system before adding or removing drawers to a system without requiring an n-level cable. Standby power is applied after all cables have been connected to the system. All available expansion ports for an SMP cable are searched. A unique ID is sent over and received by all plugged SMP cables. A list of each controller and its connected controllers is created, and a master controller is assigned. A plugging table of each controller is sent to the master controller. The master controller compares all received plugging tables to plugging rules. Errors are reported in cable plugging errors and system configuration is reported to platform management service.

Abstract: A method for accessing I/O devices in embedded control environments is provided, wherein said I/O devices are remotely attached to an embedded microprocessor. By mapping said I/O devices' resources to said microprocessor's address or memory address space, existing device drivers can be reused and the time-to-market capability is greatly improved.

Abstract: A cascaded interconnect system for providing a service interface to a memory system. The cascaded interconnect system includes a master service interface module, a service interface bus, and one or more slave service interface modules. The master service interface module and the slave interface modules are cascade interconnected via the service interface bus. Each slave service interface module is in communication with a corresponding memory module for providing a service to the memory module.

Abstract: A method for accessing I/O devices in embedded control environments is provided, wherein said I/O devices are remotely attached to an embedded microprocessor. By mapping said I/O devices' resources to said microprocessor's address or memory address space, existing device drivers can be reused and the time-to-market capability is greatly improved.

Abstract: A method is provided to adjust time delays and sequence ordering of data channels in synchronous clocked bus systems. In particular, the invention relates to a method to re-synchronize data in respective channels which have a relative delay to each other caused by different path lengths, etc., on the way from sender to receiver. Still more specifically, the invention relates to an apparatus used to eliminate those delays in order to make data usable again on the receiver side. The method can be carried out using standard microprocessors without the need for special hardware implementations. Thus the use of costly and performance intensive ASICs and signal processors can be avoided.

Abstract: Method and apparatus are provided for re-synchronizing a group of B channels in an ISDN network using the BONDING Mode 1 specification. Re-synchronization is achieved without the need to first disconnect the affected group of B channels from the network. Thus, the reliability of the bonded channels is improved while maintaining a simpler architecture than those associated with BONDING Modes 2 and 3. The solution offers improved channel reliability, improved network performance and reduced network load when channel re-synchronization becomes necessary.