Abstract: Cell-aware fault models for delay faults are created for library cells. Analog one-clock-cycle fault simulations are first performed on a transistor-level netlist of a cell to identify type one detectable defects and type two detectable defects in defects of interest. The type one detectable defects are detectable by one-clock-cycle testing and their fault models may be created based on results of the analog one-clock-cycle fault simulations. The type two detectable defects are defects for which two-cycle detection conditions may be calculated from corresponding results of the analog one-cycle fault simulations. Analog two-clock-cycle fault simulations are then performed for the rest defects in the defects of interest to determine type three detectable defects and their detection conditions. The created cell-aware fault models may be used to generate cell-aware test patterns.

Abstract: On-chip logic includes a shadow register cross-coupled with a multiple input shift/signature register (MISR). The shadow register facilitates debugging by shifting out a test signature while resetting the MISR with a fault-free signature. The on-chip logic may further include comparator circuitry to produce an output signal by comparing the test signature with the fault-free signature or by first compressing the test signature and then comparing the compressed test signature with the compressed fault-free signature.

Abstract: Cell-aware fault models for delay faults are created for library cells. Analog one-clock-cycle fault simulations are first performed on a transistor-level netlist of a cell to identify type one detectable defects and type two detectable defects in defects of interest. The type one detectable defects are detectable by one-clock-cycle testing and their fault models may be created based on results of the analog one-clock-cycle fault simulations. The type two detectable defects are defects for which two-cycle detection conditions may be calculated from corresponding results of the analog one-cycle fault simulations. Analog two-clock-cycle fault simulations are then performed for the rest defects in the defects of interest to determine type three detectable defects and their detection conditions. The created cell-aware fault models may be used to generate cell-aware test patterns.

Abstract: An integrated circuit (IC) is disclosed that comprises a circuit portion (100) having a plurality of inputs (102) and a plurality of outputs (106), the plurality of inputs being arranged to receive a test pattern in a test mode of the integrated circuit, the test pattern comprising a plurality of test vectors for feeding to the plurality of inputs in successive clock cycles. The IC also comprises a test arrangement for testing the circuit portion (100), comprising a test pattern generator (110) for generating the test pattern, masking logic (150) for masking selected outputs of the plurality of outputs (106) and a signal generator (130) coupled to the masking logic (150) for generating a masking signal triggering the masking of all of said circuit portion outputs during selected cycles of the successive clock cycles, the signal generator (130) being responsive to clock cycle selection data (s1-st).

Abstract: On-chip logic includes a shadow register cross-coupled with a multiple input shift/signature register (MISR). The shadow register facilitates debugging by shifting out a test signature while resetting the MISR with a fault-free signature. The on-chip logic may further include comparator circuitry to produce an output signal by comparing the test signature with the fault-free signature or by first compressing the test signature and then comparing the compressed test signature with the compressed fault-free signature.

Abstract: Cell-aware fault models directly address layout-based intra-cell defects. They are created by performing analog simulations on the transistor-level netlist of a library cell and then by library view synthesis. The cell-aware fault models may be used to generate cell-aware test patterns, which usually have higher defect coverage than those generated by conventional ATPG techniques. The cell-aware fault models may also be used to improve defect coverage of a set of test patterns generated by conventional ATPG techniques.

Abstract: An integrated circuit (IC) is disclosed that comprises a circuit portion (100) having a plurality of inputs (102) and a plurality of outputs (106), the plurality of inputs being arranged to receive a test pattern in a test mode of the integrated circuit, the test pattern comprising a plurality of test vectors for feeding to the plurality of inputs in successive clock cycles. The IC also comprises a test arrangement for testing the circuit portion (100), comprising a test pattern generator (110) for generating the test pattern, masking logic (150) for masking selected outputs of the plurality of outputs (106) and a signal generator (130) coupled to the masking logic (150) for generating a masking signal triggering the masking of all of said circuit portion outputs during selected cycles of the successive clock cycles, the signal generator (130) being responsive to clock cycle selection data (s1-st).