Patents by Inventor Juha Tapani Pennanen

Juha Tapani Pennanen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Transistor diagnostic circuit
    Patent number: 11563430
    Abstract: A transistor diagnostic circuit includes a protection transistor output terminal, a fault terminal, and circuitry coupled to the protection transistor output terminal and the fault terminal. The protection transistor output terminal is adapted to be coupled to a current terminal of a protection transistor. The transistor diagnostic circuit is configured to, at start-up, load the protection transistor output terminal to test the protection transistor, and to generate a fault signal at the fault terminal responsive to a voltage on the protection transistor output terminal exceeding a threshold.
    Type: Grant
    Filed: September 29, 2021
    Date of Patent: January 24, 2023
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Antti Veli Johannes Piila, Tuomas Tapani Tuikkanen, Mikko Topi Loikkanen, Jacobus Adrianus van Oevelen, Juha Tapani Pennanen
  • TRANSISTOR DIAGNOSTIC CIRCUIT
    Publication number: 20220140825
    Abstract: A transistor diagnostic circuit includes a protection transistor output terminal, a fault terminal, and circuitry coupled to the protection transistor output terminal and the fault terminal. The protection transistor output terminal is adapted to be coupled to a current terminal of a protection transistor. The transistor diagnostic circuit is configured to, at start-up, load the protection transistor output terminal to test the protection transistor, and to generate a fault signal at the fault terminal responsive to a voltage on the protection transistor output terminal exceeding a threshold.
    Type: Application
    Filed: September 29, 2021
    Publication date: May 5, 2022
    Inventors: Antti Veli Johannes Piila, Tuomas Tapani Tuikkanen, Mikko Topi Loikkanen, Jacobus Adrianus van Oevelen, Juha Tapani Pennanen
  • SYNCHRONOUS POWER STATE CONTROL SCHEME FOR MULTI-CHIP INTEGRATED POWER MANAGEMENT SOLUTION IN EMBEDDED SYSTEMS
    Publication number: 20210286421
    Abstract: Methods and apparatus for power management of embedded devices are provided. An example apparatus includes a primary power management integrated circuit (PMIC) to communicate with an embedded system to determine a power state. The example primary PMIC is to include a first power state sequence controller and a first power supply controller. The example first power state sequence controller is to drive a first power supply controller according to the power state. The example first power supply controller is to activate a first set of rails to apply power to the embedded system. The example apparatus includes a secondary PMIC including a second power state sequence controller and a second power supply controller. The example second power sequence controller is to drive a second power supply controller according to the power state. The example second power supply controller is to activate a second set of rails to apply power to the embedded system.
    Type: Application
    Filed: May 28, 2021
    Publication date: September 16, 2021
    Inventors: Pauline Poyun Wang, Juha Tapani Pennanen
  • Synchronous power state control scheme for multi-chip integrated power management solution in embedded systems
    Patent number: 11054878
    Abstract: Methods and apparatus for power management of embedded devices are provided. An example apparatus includes a primary power management integrated circuit (PMIC) to communicate with an embedded system to determine a power state. The example primary PMIC is to include a first power state sequence controller and a first power supply controller. The example first power state sequence controller is to drive a first power supply controller according to the power state. The example first power supply controller is to activate a first set of rails to apply power to the embedded system. The example apparatus includes a secondary PMIC including a second power state sequence controller and a second power supply controller. The example second power sequence controller is to drive a second power supply controller according to the power state. The example second power supply controller is to activate a second set of rails to apply power to the embedded system.
    Type: Grant
    Filed: June 29, 2018
    Date of Patent: July 6, 2021
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Pauline Poyun Wang, Juha Tapani Pennanen
  • SYNCHRONOUS POWER STATE CONTROL SCHEME FOR MULTI-CHIP INTEGRATED POWER MANAGEMENT SOLUTION IN EMBEDDED SYSTEMS
    Publication number: 20190064910
    Abstract: Methods and apparatus for power management of embedded devices are provided. An example apparatus includes a primary power management integrated circuit (PMIC) to communicate with an embedded system to determine a power state. The example primary PMIC is to include a first power state sequence controller and a first power supply controller. The example first power state sequence controller is to drive a first power supply controller according to the power state. The example first power supply controller is to activate a first set of rails to apply power to the embedded system. The example apparatus includes a secondary PMIC including a second power state sequence controller and a second power supply controller. The example second power sequence controller is to drive a second power supply controller according to the power state. The example second power supply controller is to activate a second set of rails to apply power to the embedded system.
    Type: Application
    Filed: June 29, 2018
    Publication date: February 28, 2019
    Inventors: Pauline Poyun Wang, Juha Tapani Pennanen