Patents by Inventor Juhyung NAM

Juhyung NAM has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Sub-fin leakage reduction for template strained materials
    Patent number: 11923412
    Abstract: Embodiments disclosed herein include transistor devices and methods of forming such transistor devices. In an embodiment a transistor comprises a substrate, and a fin that extends up from the substrate. In an embodiment, the fin comprises a source region, a drain region, and a channel region between the source region and the drain region. In an embodiment, the transistor further comprises and a cavity in the fin, where the cavity is below the channel region. In an embodiment, the transistor further comprises a gate stack over the fin.
    Type: Grant
    Filed: February 6, 2023
    Date of Patent: March 5, 2024
    Assignee: Intel Corporation
    Inventors: Rishabh Mehandru, Stephen Cea, Anupama Bowonder, Juhyung Nam, Willy Rachmady
  • SUB-FIN LEAKAGE REDUCTION FOR TEMPLATE STRAINED MATERIALS
    Publication number: 20230187492
    Abstract: Embodiments disclosed herein include transistor devices and methods of forming such transistor devices. In an embodiment a transistor comprises a substrate, and a fin that extends up from the substrate. In an embodiment, the fin comprises a source region, a drain region, and a channel region between the source region and the drain region. In an embodiment, the transistor further comprises and a cavity in the fin, where the cavity is below the channel region. In an embodiment, the transistor further comprises a gate stack over the fin.
    Type: Application
    Filed: February 6, 2023
    Publication date: June 15, 2023
    Inventors: Rishabh MEHANDRU, Stephen CEA, Anupama BOWONDER, Juhyung NAM, Willy RACHMADY
  • Sub-fin leakage reduction for template strained materials
    Patent number: 11600696
    Abstract: Embodiments disclosed herein include transistor devices and methods of forming such transistor devices. In an embodiment a transistor comprises a substrate, and a fin that extends up from the substrate. In an embodiment, the fin comprises a source region, a drain region, and a channel region between the source region and the drain region. In an embodiment, the transistor further comprises and a cavity in the fin, where the cavity is below the channel region. In an embodiment, the transistor further comprises a gate stack over the fin.
    Type: Grant
    Filed: June 28, 2019
    Date of Patent: March 7, 2023
    Assignee: Intel Corporation
    Inventors: Rishabh Mehandru, Stephen Cea, Anupama Bowonder, Juhyung Nam, Willy Rachmady
  • SUB-FIN LEAKAGE REDUCTION FOR TEMPLATE STRAINED MATERIALS
    Publication number: 20200411640
    Abstract: Embodiments disclosed herein include transistor devices and methods of forming such transistor devices. In an embodiment a transistor comprises a substrate, and a fin that extends up from the substrate. In an embodiment, the fin comprises a source region, a drain region, and a channel region between the source region and the drain region. In an embodiment, the transistor further comprises and a cavity in the fin, where the cavity is below the channel region. In an embodiment, the transistor further comprises a gate stack over the fin.
    Type: Application
    Filed: June 28, 2019
    Publication date: December 31, 2020
    Inventors: Rishabh MEHANDRU, Stephen CEA, Anupama BOWONDER, Juhyung NAM, Willy RACHMADY