Abstract: A technique for operating a cache memory in one of multiple modes is provided. The technique involves using an fuse dependent control stage to control the generation of read and write enable signals to redundantly implemented tag and data arrays such that a portion of the cache memory may be effectively used even if another portion of the cache memory is defective due to malfunction, yield issues, process variations, etc.

Abstract: A single-chip central processing unit (CPU) includes a processing core and a complete cache-coherent I/O system that operates asynchronously with the processing core. An internal communications protocol uses synchronizers and data buffers to transfer information between a clock domain of the processing core and a clock domain of the I/O system. The synchronizers transfer control and handshake signal between clock domains, but the data buffer transfers data without input or output synchronization circuitry for data bits. Throughput for the system is high because the processing unit has direct access to I/O system so that no delays are incurred for complex mechanisms which are commonly employed between a CPU and an external I/O chip-set. Throughput is further increased by holding data from one DMA transfer in the data buffer for use in a subsequent DMA transfer.

Abstract: A host includes a bus cache, a L1 cache and an enhanced snoop logic circuit to increase bandwidth of peripheral bus during a memory access transaction. When a device connected to the peripheral bus starts a memory read transaction, the host converts the virtual address of the memory read transaction to a physical address. The snoop logic circuit checks to see whether the physical address is in the bus cache and, if so, whether the data in the bus cache corresponding to address is valid. If there is a bus cache hit, the corresponding data is accessed from the bus cache and output onto the peripheral bus.

Abstract: A system for maintaining completion order in a multiple bus system including a bridge that posts write data includes logic units for implementing a DRAIN/EMPTY protocol. A bridge logic unit asserts an EMPTY signal when the secondary posting buffers are empty. Interrupt processing is delayed until the EMPTY signal is asserted thereby assuring that all writes are completed. If an interrupt is received and the EMPTY signal is not asserted then a DRAIN signal is asserted while the EMPTY signal is not asserted. The bridge retries all upstream write requests until EMPTY is asserted.

Abstract: A single-chip central processing unit (CPU) includes a processing core and a complete cache-coherent I/O system that operates asynchronously with the processing core. An internal communications protocol uses synchronizers and data buffers to transfer information between a clock domain of the processing core and a clock domain of the I/O system. The synchronizers transfer control and handshake signal between clock domains, but the data buffer transfers data without input or output synchronization circuitry for data bits. Throughput for the system is high because the processing unit has direct access to I/O system so that no delays are incurred for complex mechanisms which are commonly employed between a CPU and an external I/O chip-set. Throughput is further increased by holding data from one DMA transfer in the data buffer for use in a subsequent DMA transfer.