Patents by Inventor Jui-Fen CHIEN
Jui-Fen CHIEN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11830742Abstract: Embodiments disclosed herein relate generally to capping processes and structures formed thereby. In an embodiment, a conductive feature, formed in a dielectric layer, has a metallic surface, and the dielectric layer has a dielectric surface. The dielectric surface is modified to be hydrophobic by performing a surface modification treatment. After modifying the dielectric surface, a capping layer is formed on the metallic surface by performing a selective deposition process. In another embodiment, a surface of a gate structure is exposed through a dielectric layer. A capping layer is formed on the surface of the gate structure by performing a selective deposition process.Type: GrantFiled: June 29, 2022Date of Patent: November 28, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chih-Chien Chi, Pei-Hsuan Lee, Hung-Wen Su, Hsiao-Kuan Wei, Jui-Fen Chien, Hsin-Yun Hsu
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Publication number: 20230335613Abstract: Provided is a semiconductor device including a first transistor of a first type comprising a first work function layer, the first work function layer comprising a first underlying layer; and a second transistor of the first type comprising a second work function layer, the second work function layer comprising a second underlying layer. The first and second underlying layers each comprises a metal nitride layer with at least two kinds of metals, and a thickness of the first underlying layer is greater than a thickness of the second underlying layer. A method of manufacturing a gate structure for a semiconductor device is also provided.Type: ApplicationFiled: June 19, 2023Publication date: October 19, 2023Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jui-Fen Chien, Hsiao-Kuan Wei, Hsien-Ming Lee, Chin-You Hsu
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Publication number: 20230296701Abstract: In an embodiment, a device includes: a magnetoresistive random access memory cell including: a bottom electrode; a reference layer over the bottom electrode; a tunnel barrier layer over the reference layer, the tunnel barrier layer including a first composition of magnesium and oxygen; a free layer over the tunnel barrier layer, the free layer having a lesser coercivity than the reference layer; a cap layer over the free layer, the cap layer including a second composition of magnesium and oxygen, the second composition of magnesium and oxygen having a greater atomic concentration of oxygen and a lesser atomic concentration of magnesium than the first composition of magnesium and oxygen; and a top electrode over the cap layer.Type: ApplicationFiled: May 26, 2023Publication date: September 21, 2023Inventors: Jui-Fen Chien, Wei-Gang Chiu, Tsann Lin
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Patent number: 11721740Abstract: Provided is a semiconductor device including a first n-type transistor comprising a first work function layer, the first work function layer comprising a first underlying layer; and a second n-type transistor comprising a second work function layer, the second work function layer comprising a second underlying layer. The first and second underlying layers each comprises a metal nitride layer with at least two kinds of metals, and a thickness of the first underlying layer is greater than a thickness of the second underlying layer. A method of manufacturing a gate structure for a semiconductor device is also provided.Type: GrantFiled: August 9, 2021Date of Patent: August 8, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jui-Fen Chien, Hsiao-Kuan Wei, Hsien-Ming Lee, Chin-You Hsu
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Patent number: 11698423Abstract: In an embodiment, a device includes: a magnetoresistive random access memory cell including: a bottom electrode; a reference layer over the bottom electrode; a tunnel barrier layer over the reference layer, the tunnel barrier layer including a first composition of magnesium and oxygen; a free layer over the tunnel barrier layer, the free layer having a lesser coercivity than the reference layer; a cap layer over the free layer, the cap layer including a second composition of magnesium and oxygen, the second composition of magnesium and oxygen having a greater atomic concentration of oxygen and a lesser atomic concentration of magnesium than the first composition of magnesium and oxygen; and a top electrode over the cap layer.Type: GrantFiled: August 12, 2020Date of Patent: July 11, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Jui-Fen Chien, Wei-Gang Chiu, Tsann Lin
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Patent number: 11532339Abstract: A method for forming a semiconductor memory structure is provided. The method includes following operations. An interlayer is formed over a first ferromagnetic layer, wherein forming the interlayer includes following operations. A first metal film is formed by sputtering a first target material. A first oxygen treatment is conducted to the first metal film to form a first metal oxide film. A second metal oxide film is formed over the first metal oxide film by sputtering a second target material different from the first target material. A second metal film is formed by sputtering a third target material. A second oxygen treatment is conducted to the second metal film to form a third metal oxide film.Type: GrantFiled: June 15, 2020Date of Patent: December 20, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Jui-Fen Chien, Hanwen Yeh, Tsann Lin
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Publication number: 20220328309Abstract: Embodiments disclosed herein relate generally to capping processes and structures formed thereby. In an embodiment, a conductive feature, formed in a dielectric layer, has a metallic surface, and the dielectric layer has a dielectric surface. The dielectric surface is modified to be hydrophobic by performing a surface modification treatment. After modifying the dielectric surface, a capping layer is formed on the metallic surface by performing a selective deposition process. In another embodiment, a surface of a gate structure is exposed through a dielectric layer. A capping layer is formed on the surface of the gate structure by performing a selective deposition process.Type: ApplicationFiled: June 29, 2022Publication date: October 13, 2022Inventors: Chih-Chien Chi, Pei-Hsuan Lee, Hung-Wen Su, Hsiao-Kuan Wei, Jui-Fen Chien, Hsin-Yun Hsu
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Patent number: 11380542Abstract: Embodiments disclosed herein relate generally to capping processes and structures formed thereby. In an embodiment, a conductive feature, formed in a dielectric layer, has a metallic surface, and the dielectric layer has a dielectric surface. The dielectric surface is modified to be hydrophobic by performing a surface modification treatment. After modifying the dielectric surface, a capping layer is formed on the metallic surface by performing a selective deposition process. In another embodiment, a surface of a gate structure is exposed through a dielectric layer. A capping layer is formed on the surface of the gate structure by performing a selective deposition process.Type: GrantFiled: September 4, 2020Date of Patent: July 5, 2022Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chih-Chien Chi, Pei-Hsuan Lee, Hung-Wen Su, Hsiao-Kuan Wei, Jui-Fen Chien, Hsin-Yun Hsu
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Publication number: 20220050150Abstract: In an embodiment, a device includes: a magnetoresistive random access memory cell including: a bottom electrode; a reference layer over the bottom electrode; a tunnel barrier layer over the reference layer, the tunnel barrier layer including a first composition of magnesium and oxygen; a free layer over the tunnel barrier layer, the free layer having a lesser coercivity than the reference layer; a cap layer over the free layer, the cap layer including a second composition of magnesium and oxygen, the second composition of magnesium and oxygen having a greater atomic concentration of oxygen and a lesser atomic concentration of magnesium than the first composition of magnesium and oxygen; and a top electrode over the cap layer.Type: ApplicationFiled: August 12, 2020Publication date: February 17, 2022Inventors: Jui-Fen Chien, Wei-Gang Chiu, Tsann Lin
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Publication number: 20210390992Abstract: A method for forming a semiconductor memory structure is provided. The method includes following operations. An interlayer is formed over a first ferromagnetic layer, wherein forming the interlayer includes following operations. A first metal film is formed by sputtering a first target material. A first oxygen treatment is conducted to the first metal film to form a first metal oxide film. A second metal oxide film is formed over the first metal oxide film by sputtering a second target material different from the first target material. A second metal film is formed by sputtering a third target material. A second oxygen treatment is conducted to the second metal film to form a third metal oxide film.Type: ApplicationFiled: June 15, 2020Publication date: December 16, 2021Inventors: Jui-Fen Chien, Hanwen Yeh, Tsann Lin
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Publication number: 20210367056Abstract: Provided is a semiconductor device including a first n-type transistor comprising a first work function layer, the first work function layer comprising a first underlying layer; and a second n-type transistor comprising a second work function layer, the second work function layer comprising a second underlying layer. The first and second underlying layers each comprises a metal nitride layer with at least two kinds of metals, and a thickness of the first underlying layer is greater than a thickness of the second underlying layer. A method of manufacturing a gate structure for a semiconductor device is also provided.Type: ApplicationFiled: August 9, 2021Publication date: November 25, 2021Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jui-Fen Chien, Hsiao-Kuan Wei, Hsien-Ming Lee, Chin-You Hsu
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Patent number: 11088257Abstract: Provided is a semiconductor device including a first n-type fin field effect transistor (FinFET) and a second n-type FinFET. The first FinFET includes a first work function layer. The first work function layer includes a first portion of a first layer. The second n-type FinFET includes a second work function layer. The second work function layer includes a second portion of the first layer and a first portion of a second layer underlying the second portion of the first layer. A thickness of the first work function layer is less than a thickness of the second work function layer. A method of manufacturing the semiconductor device is also provided.Type: GrantFiled: May 27, 2020Date of Patent: August 10, 2021Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jui-Fen Chien, Hsiao-Kuan Wei, Hsien-Ming Lee, Chin-You Hsu
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Publication number: 20200402795Abstract: Embodiments disclosed herein relate generally to capping processes and structures formed thereby. In an embodiment, a conductive feature, formed in a dielectric layer, has a metallic surface, and the dielectric layer has a dielectric surface. The dielectric surface is modified to be hydrophobic by performing a surface modification treatment. After modifying the dielectric surface, a capping layer is formed on the metallic surface by performing a selective deposition process. In another embodiment, a surface of a gate structure is exposed through a dielectric layer. A capping layer is formed on the surface of the gate structure by performing a selective deposition process.Type: ApplicationFiled: September 4, 2020Publication date: December 24, 2020Inventors: Chih-Chien Chi, Pei-Hsuan Lee, Hung-Wen Su, Hsiao-Kuan Wei, Jui-Fen Chien, Hsin-Yun Hsu
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Patent number: 10790142Abstract: Embodiments disclosed herein relate generally to capping processes and structures formed thereby. In an embodiment, a conductive feature, formed in a dielectric layer, has a metallic surface, and the dielectric layer has a dielectric surface. The dielectric surface is modified to be hydrophobic by performing a surface modification treatment. After modifying the dielectric surface, a capping layer is formed on the metallic surface by performing a selective deposition process. In another embodiment, a surface of a gate structure is exposed through a dielectric layer. A capping layer is formed on the surface of the gate structure by performing a selective deposition process.Type: GrantFiled: January 25, 2018Date of Patent: September 29, 2020Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chih-Chien Chi, Hsiao-Kuan Wei, Hung-Wen Su, Pei-Hsuan Lee, Hsin-Yun Hsu, Jui-Fen Chien
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Publication number: 20200287014Abstract: Provided is a semiconductor device including a first n-type fin field effect transistor (FinFET) and a second n-type FinFET. The first FinFET includes a first work function layer. The first work function layer includes a first portion of a first layer. The second n-type FinFET includes a second work function layer. The second work function layer includes a second portion of the first layer and a first portion of a second layer underlying the second portion of the first layer. A thickness of the first work function layer is less than a thickness of the second work function layer. A method of manufacturing the semiconductor device is also provided.Type: ApplicationFiled: May 27, 2020Publication date: September 10, 2020Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Jui-Fen Chien, Hsiao-Kuan Wei, Hsien-Ming Lee, Chin-You Hsu
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Patent number: 10770288Abstract: Embodiments disclosed herein relate generally to capping processes and structures formed thereby. In an embodiment, a conductive feature, formed in a dielectric layer, has a metallic surface, and the dielectric layer has a dielectric surface. The dielectric surface is modified to be hydrophobic by performing a surface modification treatment. After modifying the dielectric surface, a capping layer is formed on the metallic surface by performing a selective deposition process. In another embodiment, a surface of a gate structure is exposed through a dielectric layer. A capping layer is formed on the surface of the gate structure by performing a selective deposition process.Type: GrantFiled: November 30, 2018Date of Patent: September 8, 2020Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chih-Chien Chi, Pei-Hsuan Lee, Hung-Wen Su, Hsiao-Kuan Wei, Jui-Fen Chien, Hsin-Yun Hsu
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Patent number: 10707318Abstract: Provided is a semiconductor device including a fin-type field effect transistor (FinFET). The first FinFET includes a first gate structure and the first gate structure includes a first work function layer. The first work function layer includes a first layer and a second layer. The first layer is disposed over the second layer. The second layer includes a base material and a dopant doped in the base material. The dopant comprises Al, Ta, W, or a combination thereof. The first layer and the second layer comprise different materials. A method of manufacturing the semiconductor device is also provided.Type: GrantFiled: January 23, 2018Date of Patent: July 7, 2020Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Jui-Fen Chien, Hsiao-Kuan Wei, Hsien-Ming Lee, Chin-You Hsu
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Patent number: 10515807Abstract: Methods of fabricating semiconductor devices are provided. The method includes forming a gate dielectric layer over a substrate. The method also includes depositing a first p-type work function tuning layer over the gate dielectric layer using a first atomic layer deposition (ALD) process with an inorganic precursor. The method further includes forming a second p-type work function tuning layer on the first p-type work function tuning layer using a second atomic layer deposition (ALD) process with an organic precursor. In addition, the method includes forming an n-type work function metal layer over the second p-type work function tuning layer.Type: GrantFiled: June 14, 2018Date of Patent: December 24, 2019Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Jui-Fen Chien, Chih-Hsiang Fan, Hsiao-Kuan Wei, Pohan Kung, Hsien-Ming Lee
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Publication number: 20190385855Abstract: Methods of fabricating semiconductor devices are provided. The method includes forming a gate dielectric layer over a substrate. The method also includes depositing a first p-type work function tuning layer over the gate dielectric layer using a first atomic layer deposition (ALD) process with an inorganic precursor. The method further includes forming a second p-type work function tuning layer on the first p-type work function tuning layer using a second atomic layer deposition (ALD) process with an organic precursor. In addition, the method includes forming an n-type work function metal layer over the second p-type work function tuning layer.Type: ApplicationFiled: June 14, 2018Publication date: December 19, 2019Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Jui-Fen CHIEN, Chih-Hsiang FAN, Hsiao-Kuan WEI, Pohan KUNG, Hsien-Ming LEE
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Publication number: 20190164752Abstract: Embodiments disclosed herein relate generally to capping processes and structures formed thereby. In an embodiment, a conductive feature, formed in a dielectric layer, has a metallic surface, and the dielectric layer has a dielectric surface. The dielectric surface is modified to be hydrophobic by performing a surface modification treatment. After modifying the dielectric surface, a capping layer is formed on the metallic surface by performing a selective deposition process. In another embodiment, a surface of a gate structure is exposed through a dielectric layer. A capping layer is formed on the surface of the gate structure by performing a selective deposition process.Type: ApplicationFiled: November 30, 2018Publication date: May 30, 2019Inventors: Chih-Chien Chi, Pei-Hsuan Lee, Hung-Wen Su, Hsiao-Kuan Wei, Jui-Fen Chien, Hsin-Yun Hsu