Abstract: The present disclosure provides a semiconductor structure, including a substrate having a front surface, a first semiconductor layer proximal to the front surface, a second semiconductor layer over the first semiconductor layer, a gate having a portion between the first semiconductor layer and the second semiconductor layer, a spacer between the first semiconductor layer and the second semiconductor layer, contacting the gate, and a source/drain (S/D) region, wherein the S/D region is in direct contact with a bottom surface of the second semiconductor layer, and the spacer has an upper surface interfacing with the second semiconductor layer, the upper surface including a first section proximal to the S/D region, a second section proximal to the gate, and a third section between the first section and the second section.

Abstract: A method includes forming a first fin and a second fin protruding from a frontside of a substrate, forming a gate stack over the first and second fins, forming a dielectric feature dividing the gate stack into a first segment engaging the first fin and a second segment engaging the second fin, and growing a first epitaxial feature on the first fin and a second epitaxial feature on the second fin. The dielectric feature is disposed between the first and second epitaxial features. The method also includes performing an etching process on a backside of the substrate to form a backside trench, and forming a backside via in the backside trench. The backside trench exposes the dielectric feature and the first and second epitaxial features. The backside via straddles the dielectric feature and is in electrical connection with the first and second epitaxial features.

Abstract: A semiconductor device includes a fin structure. A source/drain region is formed on the fin structure. A first gate structure is disposed over the fin structure. A source/drain contact is disposed over the source/drain region. The source/drain contact has a protruding segment that protrudes at least partially over the first gate structure. The source/drain contact electrically couples together the source/drain region and the first gate structure.

Abstract: Disclosed are a conductive film and a test component. A conductive film includes a supporting layer, a circuit layer and a protective layer. The supporting layer has a first surface and a second surface opposite to the first surface. The supporting layer supports the circuit layer. The circuit layer includes a first protruding part, a second protruding part and a connecting part. The first protruding part is disposed on the first surface. The second protruding part is disposed on the second surface. The connecting part is disposed between the first protruding part and the second protruding part. The first protruding part is connected to the second protruding part through the connecting part. The protective layer covers the first protruding part. The conductive film and the test component of the disclosed embodiments may have a buffering effect or increase the service life.

Abstract: A semiconductor device structure, along with methods of forming such, are described. The structure includes a first source/drain epitaxial feature, a second source/drain epitaxial feature disposed adjacent the first source/drain epitaxial feature, a first dielectric layer disposed between the first source/drain epitaxial feature and the second source/drain epitaxial feature, a first dielectric spacer disposed under the first dielectric layer, and a second dielectric layer disposed under the first dielectric layer and in contact with the first dielectric spacer. The second dielectric layer and the first dielectric spacer include different materials.

Abstract: The present disclosure provides a semiconductor structure, including a substrate having a front surface, a first semiconductor layer proximal to the front surface, a second semiconductor layer over the first semiconductor layer, a gate having a portion between the first semiconductor layer and the second semiconductor layer, a spacer between the first semiconductor layer and the second semiconductor layer, contacting the gate, and a source/drain (S/D) region, wherein the S/D region is in direct contact with a bottom surface of the second semiconductor layer, and the spacer has an upper surface interfacing with the second semiconductor layer, the upper surface including a first section proximal to the S/D region, a second section proximal to the gate, and a third section between the first section and the second section.

Abstract: A solar cell includes a photovoltaic substrate having a first surface and a second surface and a plurality of bus bar electrode net structures. The bus bar electrode net structures are separately disposed on the first surface, each bus bar electrode net structure includes a bus bar electrode, a plurality of finger electrodes, at least one connecting line electrode and at least one vertical finger electrode. The bus bar electrode is disposed on the first surface. The finger electrodes are separately disposed at two sides of the bus bar electrode. The connecting line electrode is disposed on the first surface. Each connecting line electrode connects with ends of at least two finger electrodes. The vertical finger electrode is disposed on the first surface, and is parallel to the bus bar electrode and disposed between the two ends of the finger electrode to connect with at least two adjacent finger electrodes.

Abstract: A solar cell with doping blocks is provided, which includes: a semiconductor substrate, an anti-reflection layer, a plurality of front electrodes, and a back electrode layer. The semiconductor substrate has a first surface, and a plurality of doping block layers is arranged under the first surface and spaced from each other. The anti-reflection layer is disposed on the doping block layer and the semiconductor substrate. The front electrodes penetrate the anti-reflection layer and are arranged on the doping block layers. The back electrode layer is disposed on a second surface of the semiconductor substrate.

Abstract: The invention discloses a motion vector estimation system and the method thereof for estimating an output motion vector for a macroblock of a frame. The motion vector estimation system is capable of selectively horizontally shifting a search window corresponding to each macroblock, so as to improve reusability of pixel data from previous search window and reduce memory bandwidth.

Abstract: The invention discloses a motion vector estimation system and the method thereof for estimating an output motion vector for a macroblock of a frame. The motion vector estimation system is capable of selectively horizontally shifting a search window corresponding to each macroblock, so as to improve reusability of pixel data from previous search window and reduce memory bandwidth.