Abstract: A static random access memory comprising a column driver, a row driver, a cell, and a control unit is disclosed. The column driver selects a first word line or a second word line. The row provides data to a first bit line and a second bit line. The data of the first bit line is opposite to that of the second bit line. The control unit controls the voltage of the cell. In normal mode, the voltage of the cell is equal to a second voltage. In stand-by mode, the voltage of the cell exceeds the second voltage.

Abstract: A stroller backrest tilting adjusting device is provided. The stroller backrest tilting adjusting device comprises two supporting straps for supporting the backrest of the stroller, each supporting strap having a fixed end attached to a frame of the stroller and a free end; a strap direction guiding unit allowing the free end of each of the straps to pass therethrough and guiding the straps' direction; and an adjusting assembly fixed to an upper portion of the backrest which is capable of adjusting the effective supporting length of the straps to thereby adjusting the tilting angle of the backrest of the stroller by operating a one-way locking member, which is disposed in the adjusting assembly and has a cam effecting portion for increasingly exerting locking force.

Abstract: A stroller backrest tilting adjusting device is provided. The stroller backrest tilting adjusting device comprises two supporting straps for supporting the backrest of the stroller, each supporting strap having a fixed end attached to a frame of the stroller and a free end; a strap direction guiding unit allowing the free end of each of the straps to pass therethrough and guiding the straps' direction; and an adjusting assembly fixed to an upper portion of the backrest which is capable of adjusting the effective supporting length of the straps to thereby adjusting the tilting angle of the backrest of the stroller by operating a one-way locking member, which is disposed in the adjusting assembly and has a cam effecting portion for increasingly exerting locking force.

Abstract: A method for performing a delay lock to generate a second clock according to a first clock and to synchronize the second clock with the first clock is provided. The method has correcting processes executed to increase or decrease, by a correction interval, a delay time between corresponding periods of the first clock and the second clock. The correction interval for a subsequent correcting process is substantially half the previous correction interval of the previous correcting process.

Abstract: A semiconductor programmable device is provided. The semiconductor programmable device comprises a P-type substrate, an N-well, an NMOS capacitor and a PMOS transistor. The N-well is formed in the P-type substrate. The NMOS capacitor is configured on the P-type substrate. The PMOS transistor is configured on the N-well. A source/drain of the PMOS transistor is electrically connected to a gate of the NMOS capacitor. A control voltage is applied to a gate of the PMOS transistor. A programming voltage is applied to the source/drain of the PMOS transistor. The programming voltage is large enough to cause a breakdown of a gate oxide layer of the NMOS capacitor. The gate oxide layer of the NMOS capacitor has a thickness identical to the gate oxide layer of the PMOS transistor.

Abstract: A method for performing a delay lock to generate a second clock according to a first clock and to synchronize the second clock with the first clock is provided. The method has correcting processes executed to increase or decrease, by a correction interval, a delay time between corresponding periods of the first clock and the second clock. The correction interval for a subsequent correcting process is substantially half the previous correction interval of the previous correcting process.

Abstract: A DRAM circuitry includes a DRAM cell that is connected at a first end to a bit line, at a second end to a plate line, and at a third end to a word line, and a sensing amplifier that is electrically connected to the DRAM cell for refreshing the DRAM cell and reading data from the DRAM cell. The sensing amplifier can change a potential of the bit line and a potential of the plate line to write data into the DRAM cell when the word line is turned on.

Abstract: A memory device has an output buffer. The output buffer is electrically connected to a data output port of a sense amplifier of the memory device for amplifying an output signal from the data output port. The output buffer has a detector for producing a control signal according to the output signal from the data output port, and an amplifier for amplifying the output signal from the data output port. The amplifier has an input port electrically connected to the data output port for accepting the output signal from the data output port, and a control terminal electrically connected to the output terminal of the detector for accepting the control signal from the detector to control operations of the amplifier. When the detector produces the control signal and transmits the control signal to the control terminal of the amplifier, the amplifier begins amplifying the output signal transmitted from the data output port to the input port of the amplifier.

Abstract: A apparatus uses a test method to perform burn-in testing of a static random access memory that has a plurality of word lines, a plurality of first bit lines, a plurality of second bit lines, and a plurality of memory cells for storing data. Each of the memory cells is coupled to a corresponding word line, a corresponding first bit line, a corresponding second bit line, and a power supply that is used to apply a working voltage to the memory cell to drive the memory cell. When the apparatus tests the static random access memory, the apparatus adjusts the working voltage according to a potential of the word lines and voltage gaps between the first bit lines and the second bit lines.