Patents by Inventor Jui-Ming Yang
Jui-Ming Yang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11990378Abstract: An embodiment method includes: forming fins extending from a semiconductor substrate; depositing an inter-layer dielectric (ILD) layer on the fins; forming masking layers on the ILD layer; forming a cut mask on the masking layers, the cut mask including a first dielectric material, the cut mask having first openings exposing the masking layers, each of the first openings surrounded on all sides by the first dielectric material; forming a line mask on the cut mask and in the first openings, the line mask having slot openings, the slot openings exposing portions of the cut mask and portions of the masking layers, the slot openings being strips extending perpendicular to the fins; patterning the masking layers by etching the portions of the masking layers exposed by the first openings and the slot openings; and etching contact openings in the ILD layer using the patterned masking layers as an etching mask.Type: GrantFiled: March 24, 2023Date of Patent: May 21, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chien-Yuan Chen, Jui-Ping Lin, Chen-Ming Lee, Fu-Kai Yang, Mei-Yun Wang
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Publication number: 20240154015Abstract: A method includes forming a first fin and a second fin protruding from a frontside of a substrate, forming a gate stack over the first and second fins, forming a dielectric feature dividing the gate stack into a first segment engaging the first fin and a second segment engaging the second fin, and growing a first epitaxial feature on the first fin and a second epitaxial feature on the second fin. The dielectric feature is disposed between the first and second epitaxial features. The method also includes performing an etching process on a backside of the substrate to form a backside trench, and forming a backside via in the backside trench. The backside trench exposes the dielectric feature and the first and second epitaxial features. The backside via straddles the dielectric feature and is in electrical connection with the first and second epitaxial features.Type: ApplicationFiled: March 22, 2023Publication date: May 9, 2024Inventors: Jui-Lin CHEN, Hsin-Wen SU, Chih-Ching WANG, Chen-Ming LEE, Chung-I YANG, Yi-Feng TING, Jon-Hsu HO, Lien-Jung HUNG, Ping-Wei WANG
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Publication number: 20240147711Abstract: The present disclosure provides a memory device, a semiconductor device, and a method of operating a memory device. A memory device includes a memory cell, a bit line, a word line, a select transistor, a fuse element, and a heater. The bit line is connected to the memory cell. The word line is connected to the memory cell. The select transistor is disposed in the memory cell. A gate of the select transistor is connected to the word line. The fuse element is disposed in the memory cell. The fuse element is connected to the bit line and the select transistor. The heater is configured to heat the fuse element.Type: ApplicationFiled: January 4, 2024Publication date: May 2, 2024Inventors: PERNG-FEI YUH, YIH WANG, MENG-SHENG CHANG, JUI-CHE TSAI, KU-FENG LIN, YU-WEI LIN, KEH-JENG CHANG, CHANSYUN DAVID YANG, SHAO-TING WU, SHAO-YU CHOU, PHILEX MING-YAN FAN, YOSHITAKA YAMAUCHI, TZU-HSIEN YANG
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Patent number: 11965883Abstract: Provided are point of care sensor systems that include portable readers and disposable cartridges for receiving and analyzing samples. A cartridge may be equipped with one or more sensor channels, each containing one or more sensors. After providing a sample to a cartridge, the cartridge can be inserted into a reader, which can interact with the cartridge to perform on-cartridge sensing and receive signals indicating the presence and/or quantity of one or more targets in the sample. Examples of cartridges can include cardiac panels, sepsis panels and the like. In some embodiments, the same sensor hardware may be configured for multiple measurements of different targets conducted at different time frames. Also provided herein are novel on-cartridge solid and liquid reagent storage and delivery mechanisms.Type: GrantFiled: November 7, 2019Date of Patent: April 23, 2024Assignee: Nanomix, Inc.Inventors: Bradley N. Johnson, Jui-Ming Yang, Kanchan A. Joshi, Ray R. Radtkey, Garrett Gruener, Sergei Skarupo
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Publication number: 20240130040Abstract: Disclosed are a conductive film and a test component. A conductive film includes a supporting layer, a circuit layer and a protective layer. The supporting layer has a first surface and a second surface opposite to the first surface. The supporting layer supports the circuit layer. The circuit layer includes a first protruding part, a second protruding part and a connecting part. The first protruding part is disposed on the first surface. The second protruding part is disposed on the second surface. The connecting part is disposed between the first protruding part and the second protruding part. The first protruding part is connected to the second protruding part through the connecting part. The protective layer covers the first protruding part. The conductive film and the test component of the disclosed embodiments may have a buffering effect or increase the service life.Type: ApplicationFiled: September 7, 2023Publication date: April 18, 2024Applicant: Innolux CorporationInventors: Ker-Yih Kao, Kuang-Ming Fan, Chia-Lin Yang, Jui-Jen Yueh, Ju-Li Wang
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Patent number: 11942145Abstract: The present disclosure describes a method for memory cell placement. The method can include placing a memory cell region in a layout area and placing a well pick-up region and a first power supply routing region along a first side of the memory cell region. The method also includes placing a second power supply routing region and a bitline jumper routing region along a second side of the memory cell region, where the second side is on an opposite side to that of the first side. The method further includes placing a device region along the second side of the memory cell region, where the bitline jumper routing region is between the second power supply routing region and the device region.Type: GrantFiled: May 6, 2022Date of Patent: March 26, 2024Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chih-Chuan Yang, Jui-Wen Chang, Feng-Ming Chang, Kian-Long Lim, Kuo-Hsiu Hsu, Lien Jung Hung, Ping-Wei Wang
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Patent number: 11239082Abstract: A method for fabricating semiconductor device includes the steps of first forming a gate dielectric layer on a substrate; forming a gate material layer on the gate dielectric layer, and removing part of the gate material layer and part of the gate dielectric layer to form a gate electrode, in which a top surface of the gate dielectric layer adjacent to two sides of the gate electrode is lower than a top surface of the gate dielectric layer between the gate electrode and the substrate. Next, a first mask layer is formed on the gate dielectric layer and the gate electrode, part of the first mask layer and part of the gate dielectric layer are removed to form a first spacer, a second mask layer is formed on the substrate and the gate electrode, and part of the second mask layer is removed to forma second spacer.Type: GrantFiled: June 11, 2019Date of Patent: February 1, 2022Assignee: UNITED MICROELECTRONICS CORP.Inventors: I-Fan Chang, Yen-Liang Wu, Wen-Tsung Chang, Jui-Ming Yang, Jie-Ning Yang, Chi-Ju Lee, Chun-Ting Chiang, Bo-Yu Su, Chih-Wei Lin, Dien-Yang Lu
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Publication number: 20200232981Abstract: Provided are point of care sensor systems that include portable readers and disposable cartridges for receiving and analyzing samples. A cartridge may be equipped with one or more sensor channels, each containing one or more sensors. After providing a sample to a cartridge, the cartridge can be inserted into a reader, which can interact with the cartridge to perform on-cartridge sensing and receive signals indicating the presence and/or quantity of one or more targets in the sample. Examples of cartridges can include cardiac panels, sepsis panels and the like. In some embodiments, the same sensor hardware may be configured for multiple measurements of different targets conducted at different time frames. Also provided herein are novel on-cartridge solid and liquid reagent storage and delivery mechanisms.Type: ApplicationFiled: November 7, 2019Publication date: July 23, 2020Applicant: Nanomix, Inc.Inventors: Bradley N. Johnson, Jui-Ming Yang, Kanchan A. Joshi, Ray R. Radtkey, Garrett Gruener, Sergei Skarupo
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Patent number: 10520501Abstract: Provided are point of care sensor systems that include portable readers and disposable cartridges for receiving and analyzing samples. A cartridge may be equipped with one or more sensor channels, each containing one or more sensors. After providing a sample to a cartridge, the cartridge can be inserted into a reader, which can interact with the cartridge to perform on-cartridge sensing and receive signals indicating the presence and/or quantity of one or more targets in the sample. Examples of cartridges can include cardiac panels, sepsis panels and the like. In some embodiments, the same sensor hardware may be configured for multiple measurements of different targets conducted at different time frames. Also provided herein are novel on-cartridge solid and liquid reagent storage and delivery mechanisms.Type: GrantFiled: September 9, 2016Date of Patent: December 31, 2019Assignee: Nanomix, Inc.Inventors: Bradley N. Johnson, Jui-Ming Yang, Kanchan A. Joshi, Ray R. Radtkey, Garrett Gruener, Sergei Skarupo
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Patent number: 10468493Abstract: The present invention provides a method of manufacturing a gate stack structure. The method comprises providing a substrate. A dielectric layer is then formed on the substrate and a gate trench is formed in the dielectric layer. A bottom barrier layer, a first work function metal layer and a top barrier layer are formed in the gate trench in sequence. Afterwards, a silicon formation layer is formed on the top barrier layer and filling the gate trench. A planarization process is performed, to remove a portion of the silicon formation layer, a portion of the bottom barrier layer, a portion of the first work function metal layer, and a portion of the top barrier layer. Next, the remaining silicon formation layer is removed completely, and a conductive layer is filled in the gate trench.Type: GrantFiled: December 6, 2018Date of Patent: November 5, 2019Assignee: UNITED MICROELECTRONICS CORP.Inventors: Chun-Ting Chiang, Chi-Ju Lee, Chih-Wei Lin, Bo-Yu Su, Yen-Liang Wu, Wen-Tsung Chang, Jui-Ming Yang, I-Fan Chang
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Publication number: 20190295849Abstract: A method for fabricating semiconductor device includes the steps of first forming a gate dielectric layer on a substrate; forming a gate material layer on the gate dielectric layer, and removing part of the gate material layer and part of the gate dielectric layer to form a gate electrode, in which a top surface of the gate dielectric layer adjacent to two sides of the gate electrode is lower than a top surface of the gate dielectric layer between the gate electrode and the substrate. Next, a first mask layer is formed on the gate dielectric layer and the gate electrode, part of the first mask layer and part of the gate dielectric layer are removed to form a first spacer, a second mask layer is formed on the substrate and the gate electrode, and part of the second mask layer is removed to forma second spacer.Type: ApplicationFiled: June 11, 2019Publication date: September 26, 2019Inventors: I-Fan Chang, Yen-Liang Wu, Wen-Tsung Chang, Jui-Ming Yang, Jie-Ning Yang, Chi-Ju Lee, Chun-Ting Chiang, Bo-Yu Su, Chih-Wei Lin, Dien-Yang Lu
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Patent number: 10388749Abstract: A semiconductor device includes a substrate, a gate structure, a spacer, a mask layer, and at least one void. The gate structure is disposed on the substrate, and the gate structure includes a metal gate electrode. The spacer is disposed on sidewalls of the gate structure, and a topmost surface of the spacer is higher than a topmost surface of the metal gate electrode. The mask layer is disposed on the gate structure. At least one void is disposed in the mask layer and disposed between the metal gate electrode and the spacer.Type: GrantFiled: July 23, 2018Date of Patent: August 20, 2019Assignee: UNITED MICROELECTRONICS CORP.Inventors: Yen-Liang Wu, Wen-Tsung Chang, Jui-Ming Yang, I-Fan Chang, Chun-Ting Chiang, Chih-Wei Lin, Bo-Yu Su, Chi-Ju Lee
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Patent number: 10366896Abstract: A method for fabricating semiconductor device includes the steps of first forming a gate dielectric layer on a substrate; forming a gate material layer on the gate dielectric layer, and removing part of the gate material layer and part of the gate dielectric layer to form a gate electrode, in which a top surface of the gate dielectric layer adjacent to two sides of the gate electrode is lower than a top surface of the gate dielectric layer between the gate electrode and the substrate. Next, a first mask layer is formed on the gate dielectric layer and the gate electrode, part of the first mask layer and part of the gate dielectric layer are removed to form a first spacer, a second mask layer is formed on the substrate and the gate electrode, and part of the second mask layer is removed to form a second spacer.Type: GrantFiled: August 28, 2017Date of Patent: July 30, 2019Assignee: UNITED MICROELECTRONICS CORP.Inventors: I-Fan Chang, Yen-Liang Wu, Wen-Tsung Chang, Jui-Ming Yang, Jie-Ning Yang, Chi-Ju Lee, Chun-Ting Chiang, Bo-Yu Su, Chih-Wei Lin, Dien-Yang Lu
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Publication number: 20190109202Abstract: The present invention provides a method of manufacturing a gate stack structure. The method comprises providing a substrate. A dielectric layer is then formed on the substrate and a gate trench is formed in the dielectric layer. A bottom barrier layer, a first work function metal layer and a top barrier layer are formed in the gate trench in sequence. Afterwards, a silicon formation layer is formed on the top barrier layer and filling the gate trench. A planarization process is performed, to remove a portion of the silicon formation layer, a portion of the bottom barrier layer, a portion of the first work function metal layer, and a portion of the top barrier layer. Next, the remaining silicon formation layer is removed completely, and a conductive layer is filled in the gate trench.Type: ApplicationFiled: December 6, 2018Publication date: April 11, 2019Inventors: Chun-Ting Chiang, Chi-Ju Lee, Chih-Wei Lin, Bo-Yu Su, Yen-Liang Wu, Wen-Tsung Chang, Jui-Ming Yang, I-Fan Chang
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Publication number: 20190043725Abstract: A method for fabricating semiconductor device includes the steps of first forming a gate dielectric layer on a substrate; forming a gate material layer on the gate dielectric layer, and removing part of the gate material layer and part of the gate dielectric layer to form a gate electrode, in which a top surface of the gate dielectric layer adjacent to two sides of the gate electrode is lower than a top surface of the gate dielectric layer between the gate electrode and the substrate. Next, a first mask layer is formed on the gate dielectric layer and the gate electrode, part of the first mask layer and part of the gate dielectric layer are removed to form a first spacer, a second mask layer is formed on the substrate and the gate electrode, and part of the second mask layer is removed to form a second spacer.Type: ApplicationFiled: August 28, 2017Publication date: February 7, 2019Inventors: I-Fan Chang, Yen-Liang Wu, Wen-Tsung Chang, Jui-Ming Yang, Jie-Ning Yang, Chi-Ju Lee, Chun-Ting Chiang, Bo-Yu Su, Chih-Wei Lin, Dien-Yang Lu
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Patent number: 10186594Abstract: The present invention provides a method of manufacturing a gate stack structure. The method comprises providing a substrate. A dielectric layer is then formed on the substrate and a gate trench is formed in the dielectric layer. A bottom barrier layer, a first work function metal layer and a top barrier layer are formed in the gate trench in sequence. Afterwards, a silicon formation layer is formed on the top barrier layer and filling the gate trench. A planarization process is performed, to remove a portion of the silicon formation layer, a portion of the bottom barrier layer, a portion of the first work function metal layer, and a portion of the top barrier layer. Next, the remaining silicon formation layer is removed completely, and a conductive layer is filled in the gate trench.Type: GrantFiled: July 4, 2017Date of Patent: January 22, 2019Assignee: UNITED MICROELECTRONICS CORP.Inventors: Chun-Ting Chiang, Chi-Ju Lee, Chih-Wei Lin, Bo-Yu Su, Yen-Liang Wu, Wen-Tsung Chang, Jui-Ming Yang, I-Fan Chang
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Publication number: 20190006484Abstract: A semiconductor device includes a substrate, a gate structure, a spacer, a mask layer, and at least one void. The gate structure is disposed on the substrate, and the gate structure includes a metal gate electrode. The spacer is disposed on sidewalls of the gate structure, and a topmost surface of the spacer is higher than a topmost surface of the metal gate electrode. The mask layer is disposed on the gate structure. At least one void is disposed in the mask layer and disposed between the metal gate electrode and the spacer.Type: ApplicationFiled: July 23, 2018Publication date: January 3, 2019Inventors: Yen-Liang Wu, Wen-Tsung Chang, Jui-Ming Yang, I-Fan Chang, Chun-Ting Chiang, Chih-Wei Lin, Bo-Yu Su, Chi-Ju Lee
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Patent number: 10170573Abstract: A semiconductor device includes a substrate, a metal gate on the substrate, and a first inter-layer dielectric (ILD) layer around the metal gate. A top surface of the metal gate is lower than a top surface of the ILD layer thereby forming a recessed region atop the metal gate. A mask layer is disposed in the recessed region. A void is formed in the mask layer within the recessed region. A second ILD layer is disposed on the mask layer and the first ILD layer. A contact hole extends into the second ILD layer and the mask layer. The contact hole exposes the top surface of the metal gate and communicates with the void. A conductive layer is disposed in the contact hole and the void.Type: GrantFiled: October 12, 2017Date of Patent: January 1, 2019Assignee: UNITED MICROELECTRONICS CORP.Inventors: Chun-Ting Chiang, Jie-Ning Yang, Chi-Ju Lee, Chih-Wei Lin, Bo-Yu Su, Yen-Liang Wu, I-Fan Chang, Jui-Ming Yang, Wen-Tsung Chang
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Publication number: 20180358448Abstract: The present invention provides a method of manufacturing a gate stack structure. The method comprises providing a substrate. A dielectric layer is then formed on the substrate and a gate trench is formed in the dielectric layer. A bottom barrier layer, a first work function metal layer and a top barrier layer are formed in the gate trench in sequence. Afterwards, a silicon formation layer is formed on the top barrier layer and filling the gate trench. A planarization process is performed, to remove a portion of the silicon formation layer, a portion of the bottom barrier layer, a portion of the first work function metal layer, and a portion of the top barrier layer. Next, the remaining silicon formation layer is removed completely, and a conductive layer is filled in the gate trench.Type: ApplicationFiled: July 4, 2017Publication date: December 13, 2018Inventors: Chun-Ting Chiang, Chi-Ju Lee, Chih-Wei Lin, Bo-Yu Su, Yen-Liang Wu, Wen-Tsung Chang, Jui-Ming Yang, I-Fan Chang
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Patent number: 10098224Abstract: Reinforcement components for electrical connections with limited accessibility Shield structures with reduced spacing between adjacent insulation components and systems and methods for making the same are provided. In some embodiments, a reinforcement component may be compressed between two portions of a first electronic component in order to deform the reinforcement component for filling in a void between the reinforcement component and a coupling formed between the first electronic component and a second electronic component. The first electronic component may be a flexible circuit component that may be folded over the reinforcement component prior to the reinforcement component being compressed. This may enable the reinforcement component to be effectively positioned with respect to the first electronic component prior to being deformed for reinforcing one or more couplings made between the first electronic component and the second electronic component.Type: GrantFiled: January 15, 2018Date of Patent: October 9, 2018Assignee: APPLE INC.Inventors: Yindar Chuo, Nathan K. Gupta, Po-Jui Chen, Wei Lin, Wei-Hao Sun, Jui-Ming Yang