Patents by Inventor Jui-Yao Yang
Jui-Yao Yang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11650642Abstract: A request for an estimated temperature of a memory sub-system including multiple components can be received. A set of component temperature values based on temperature measurements at the components can be identified. A subset of the component temperature values can be generated by removing one or more of the component temperature values from the set of component temperature values based on one or more criteria. The estimated temperature value that estimates the temperature of the memory sub-system can be generated using the subset of the component temperature values.Type: GrantFiled: December 3, 2018Date of Patent: May 16, 2023Assignee: Micron Technology, Inc.Inventors: David A. Holmstrom, Jui-Yao Yang, William Akin
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Patent number: 10949091Abstract: The present disclosure includes methods and devices for a memory controller. In one or more embodiments, a memory controller includes a plurality of back end channels, and a command queue communicatively coupled to the plurality of back end channels. The command queue is configured to hold host commands received from a host. Circuitry is configured to generate a number of back end commands at least in response to a number of the host commands in the command queue, and distribute the number of back end commands to a number of the plurality of back end channels.Type: GrantFiled: May 14, 2019Date of Patent: March 16, 2021Assignee: Micron Technology, Inc.Inventors: Mehdi Asnaashari, Yu-Song Liao, Jui-Yao Yang, Siamack Nemazie
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Patent number: 10768857Abstract: A storage system, includes a controller and a solid state disk. The controller creates multiple segments in advance, selects a first die from the multiple dies, selects a first segment from the multiple segments, determines an available offset of the first segment, generates a write request, where the write request includes a write address, target data, and a data length of the target data, and the write address includes an identifier of a channel coupled to the first die, an identifier of the first die, an identifier of the first segment, and the available offset, and sends the write request to the solid state disk. The solid state disk receives the write request, and stores the target data according to the write address and the data length.Type: GrantFiled: April 16, 2018Date of Patent: September 8, 2020Assignee: HUAWEI TECHNOLOGIES CO., LTD.Inventors: Meng Zhou, Kun Tang, Jui-Yao Yang, Jea Woong Hyun
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Publication number: 20200174535Abstract: A request for an estimated temperature of a memory sub-system including multiple components can be received. A set of component temperature values based on temperature measurements at the components can be identified. A subset of the component temperature values can be generated by removing one or more of the component temperature values from the set of component temperature values based on one or more criteria. The estimated temperature value that estimates the temperature of the memory sub-system can be generated using the subset of the component temperature values.Type: ApplicationFiled: December 3, 2018Publication date: June 4, 2020Inventors: David A. Holmstrom, Jui-Yao Yang, William Akin
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Publication number: 20190265889Abstract: The present disclosure includes methods and devices for a memory controller. In one or more embodiments, a memory controller includes a plurality of back end channels, and a command queue communicatively coupled to the plurality of back end channels. The command queue is configured to hold host commands received from a host. Circuitry is configured to generate a number of back end commands at least in response to a number of the host commands in the command queue, and distribute the number of back end commands to a number of the plurality of back end channels.Type: ApplicationFiled: May 14, 2019Publication date: August 29, 2019Inventors: Mehdi Asnaashari, Yu-Song Liao, Jui-Yao Yang, Siamack Nemazie
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Patent number: 10331351Abstract: The present disclosure includes methods and devices for a memory controller. In one or more embodiments, a memory controller includes a plurality of back end channels, and a command queue communicatively coupled to the plurality of back end channels. The command queue is configured to hold host commands received from a host. Circuitry is configured to generate a number of back end commands at least in response to a number of the host commands in the command queue, and distribute the number of back end commands to a number of the plurality of back end channels.Type: GrantFiled: April 7, 2015Date of Patent: June 25, 2019Assignee: Micron Technology, Inc.Inventors: Mehdi Asnaashari, Yu-Song Liao, Jui-Yao Yang, Siamack Nemazie
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Patent number: 10109352Abstract: Systems and methods for managing data retention in a solid-state storage system utilizing data retention flag bytes are disclosed. A data storage device includes a non-volatile memory comprising a plurality of non-volatile memory devices and a controller configured to write data to a memory unit of the non-volatile memory array and write a data retention flag value indicating a number of bits of the written data programmed in a first of a plurality of logical states. The controller is further configured to read the data and determine a number of bits having the first of the plurality of logical states in the read data, and determine a difference between the number of bits of the written data programmed in the first logical state and the number of bits having the first logical state in the read data. The difference is used to determine data retention characteristics of the non-volatile memory.Type: GrantFiled: April 10, 2017Date of Patent: October 23, 2018Assignee: Western Digital Technologies, Inc.Inventors: Dengtao Zhao, Yongke Sun, Haibo Li, Jui-Yao Yang, Kroum Stoev
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Publication number: 20180232181Abstract: A storage system, includes a controller and a solid state disk. The controller creates multiple segments in advance, selects a first die from the multiple dies, selects a first segment from the multiple segments, determines an available offset of the first segment, generates a write request, where the write request includes a write address, target data, and a data length of the target data, and the write address includes an identifier of a channel coupled to the first die, an identifier of the first die, an identifier of the first segment, and the available offset, and sends the write request to the solid state disk. The solid state disk receives the write request, and stores the target data according to the write address and the data length.Type: ApplicationFiled: April 16, 2018Publication date: August 16, 2018Inventors: Meng Zhou, Kun Tang, Jui-Yao Yang, Jea Woong Hyun
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Patent number: 9952939Abstract: In some embodiments of the present invention, a data storage system includes a controller and a non-volatile memory array having a plurality of memory pages. The controller performs a method that efficiently resolves the lower page corruption problem. In one embodiment, the method selects programmed lower page(s) for which paired upper page(s) have not been programmed, reads data from those selected lower page(s), corrects the read data, and reprograms the read data into those lower page(s). Since the number of lower pages in this condition is typically low (e.g., several pages in a block with hundreds or thousands of pages), this is a much more efficient method than reprogramming the entire block. In another embodiment, a similar reprogramming method is applied as a data recovery scheme in situations in which only lower pages are programmed (e.g., SLC memory, MLC memory in SLC mode, etc.).Type: GrantFiled: April 30, 2015Date of Patent: April 24, 2018Assignee: Western Digital Technologies, Inc.Inventors: Yongke Sun, Dengtao Zhao, Jui-Yao Yang
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Publication number: 20170352423Abstract: Systems and methods for managing data retention in a solid-state storage system utilizing data retention flag bytes are disclosed. A data storage device includes a non-volatile memory comprising a plurality of non-volatile memory devices and a controller configured to write data to a memory unit of the non-volatile memory array and write a data retention flag value indicating a number of bits of the written data programmed in a first of a plurality of logical states. The controller is further configured to read the data and determine a number of bits having the first of the plurality of logical states in the read data, and determine a difference between the number of bits of the written data programmed in the first logical state and the number of bits having the first logical state in the read data. The difference is used to determine data retention characteristics of the non-volatile memory.Type: ApplicationFiled: April 10, 2017Publication date: December 7, 2017Inventors: Dengtao Zhao, Yongke Sun, Haibo Li, Jui-Yao Yang, Kroum Stoev
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Patent number: 9620220Abstract: Systems and methods for managing data retention in a solid-state storage system utilizing data retention flag bytes are disclosed. A data storage device includes a non-volatile memory comprising a plurality of non-volatile memory devices and a controller configured to write data to a memory unit of the non-volatile memory array and write a data retention flag value indicating a number of bits of the written data programmed in a first of a plurality of logical states. The controller is further configured to read the data and determine a number of bits having the first of the plurality of logical states in the read data, and determine a difference between the number of bits of the written data programmed in the first logical state and the number of bits having the first logical state in the read data. The difference is used to determine data retention characteristics of the non-volatile memory.Type: GrantFiled: February 12, 2016Date of Patent: April 11, 2017Assignee: Western Digital Technologies, Inc.Inventors: Dengtao Zhao, Yongke Sun, Haibo Li, Jui-Yao Yang, Kroum Stoev
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Publication number: 20160163392Abstract: Systems and methods for managing data retention in a solid-state storage system utilizing data retention flag bytes are disclosed. A data storage device includes a non-volatile memory comprising a plurality of non-volatile memory devices and a controller configured to write data to a memory unit of the non-volatile memory array and write a data retention flag value indicating a number of bits of the written data programmed in a first of a plurality of logical states. The controller is further configured to read the data and determine a number of bits having the first of the plurality of logical states in the read data, and determine a difference between the number of bits of the written data programmed in the first logical state and the number of bits having the first logical state in the read data. The difference is used to determine data retention characteristics of the non-volatile memory.Type: ApplicationFiled: February 12, 2016Publication date: June 9, 2016Inventors: Dengtao ZHAO, Yongke SUN, Haibo LI, Jui-Yao YANG, Kroum STOEV
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Patent number: 9263136Abstract: Systems and methods for managing data retention in a solid-state storage system utilizing data retention flag bytes are disclosed. A data storage device includes a non-volatile memory comprising a plurality of non-volatile memory devices and a controller configured to write data to a memory unit of the non-volatile memory array and write a data retention flag value indicating a number of bits of the written data programmed in a first of a plurality of logical states. The controller is further configured to read the data and determine a number of bits having the first of the plurality of logical states in the read data, and determine a difference between the number of bits of the written data programmed in the first logical state and the number of bits having the first logical state in the read data. The difference is used to determine data retention characteristics of the non-volatile memory.Type: GrantFiled: November 26, 2013Date of Patent: February 16, 2016Assignee: Western Digital Technologies, Inc.Inventors: Dengtao Zhao, Yongke Sun, Haibo Li, Jui-Yao Yang, Kroum Stoev
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Patent number: 9177638Abstract: A data storage device may comprise a plurality of Multi-Level Cell (MLC) non-volatile memory devices comprising a plurality of lower pages and a corresponding plurality of higher-order pages. A controller may be configured to write data to and read data from the plurality of lower pages and the corresponding plurality of higher-order pages. A buffer may be coupled to the controller, which may be configured to accumulate data to be written to the MLC non-volatile memory devices, allocate space in the buffer and write the accumulated data to the allocated space. At least a portion of the accumulated data may be written in a lower page of the MLC non-volatile memory devices and the space in the buffer that stores data written to the lower page may be de-allocated when all higher-order pages corresponding to the lower page have been written in the MLC non-volatile memory devices.Type: GrantFiled: November 13, 2012Date of Patent: November 3, 2015Assignees: Western Digital Technologies, Inc., Skyera, LLCInventors: Radoslav Danilak, Rodney N. Mullendore, Andrew J. Tomlin, Justin Jones, Jui-Yao Yang
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Publication number: 20150220386Abstract: The present disclosure includes methods, devices, and systems for data integrity in memory controllers. One memory controller embodiment includes a host interface and first error detection circuitry coupled to the host interface. The memory controller can include a memory interface and second error detection circuitry coupled to the memory interface. The first error detection circuitry can be configured to calculate error detection data for data received from the host interface and to check the integrity of data transmitted to the host interface. The second error detection circuitry can be configured to calculate error correction data for data and first error correction data transmitted to the memory interface and to check integrity of data and first error correction data received from the memory interface.Type: ApplicationFiled: April 16, 2015Publication date: August 6, 2015Applicant: Micron Technology, Inc.Inventors: Mehdi Asnaashari, Ronald Yamada, Siamack Nemazie, Jui-Yao Yang
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Publication number: 20150212734Abstract: The present disclosure includes methods and devices for a memory controller. In one or more embodiments, a memory controller includes a plurality of back end channels, and a command queue communicatively coupled to the plurality of back end channels. The command queue is configured to hold host commands received from a host. Circuitry is configured to generate a number of back end commands at least in response to a number of the host commands in the command queue, and distribute the number of back end commands to a number of the plurality of back end channels.Type: ApplicationFiled: April 7, 2015Publication date: July 30, 2015Inventors: Mehdi Asnaashari, Yu-Song Liao, Jui-Yao Yang, Siamack Nemazie
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Patent number: 9032271Abstract: In some embodiments of the present invention, a data storage system includes a controller and a non-volatile memory array having a plurality of memory pages. The controller performs a method that efficiently resolves the lower page corruption problem. In one embodiment, the method selects programmed lower page(s) for which paired upper page(s) have not been programmed, reads data from those selected lower page(s), corrects the read data, and reprograms the read data into those lower page(s). Since the number of lower pages in this condition is typically low (e.g., several pages in a block with hundreds or thousands of pages), this is a much more efficient method than reprogramming the entire block. In another embodiment, a similar reprogramming method is applied as a data recovery scheme in situations in which only lower pages are programmed (e.g., SLC memory, MLC memory in SLC mode, etc.).Type: GrantFiled: December 7, 2012Date of Patent: May 12, 2015Assignee: Western Digital Technologies, Inc.Inventors: Yongke Sun, Dengtao Zhao, Jui-Yao Yang
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Patent number: 9015356Abstract: The present disclosure includes methods and devices for a memory controller. In one or more embodiments, a memory controller includes a plurality of back end channels, and a command queue communicatively coupled to the plurality of back end channels. The command queue is configured to hold host commands received from a host. Circuitry is configured to generate a number of back end commands at least in response to a number of the host commands in the command queue, and distribute the number of back end commands to a number of the plurality of back end channels.Type: GrantFiled: May 2, 2014Date of Patent: April 21, 2015Assignee: Micron TechnologyInventors: Mehdi Asnaashari, Yu-Song Liao, Jui-Yao Yang, Siamack Nemazie
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Patent number: 9015553Abstract: The present disclosure includes methods, devices, and systems for data integrity in memory controllers. One memory controller embodiment includes a host interface and first error detection circuitry coupled to the host interface. The memory controller can include a memory interface and second error detection circuitry coupled to the memory interface. The first error detection circuitry can be configured to calculate error detection data for data received from the host interface and to check the integrity of data transmitted to the host interface. The second error detection circuitry can be configured to calculate error correction data for data and first error correction data transmitted to the memory interface and to check integrity of data and first error correction data received from the memory interface.Type: GrantFiled: June 18, 2013Date of Patent: April 21, 2015Assignee: Round Rock Research, LLCInventors: Mehdi Asnaashari, Ronald Yamada, Siamack Nemazie, Jui-Yao Yang
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Patent number: 8966343Abstract: A solid-state storage retention monitor determines whether user data in a solid-state device is in need of a scrubbing operation. One or more reference blocks may be programmed with a known data pattern, wherein the reference block(s) experiences substantially similar P/E cycling, storage temperature, storage time, and other conditions as the user blocks. The reference blocks may therefore effectively represent data retention properties of the user blocks and provide information regarding whether/when a data refreshing operation is needed.Type: GrantFiled: August 21, 2012Date of Patent: February 24, 2015Assignee: Western Digital Technologies, Inc.Inventors: Mei-Man L. Syu, Jui-Yao Yang, Dengtao Zhao