Patents by Inventor Julia Elvidge
Julia Elvidge has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7509601Abstract: A design analysis workstation for performing design analysis of integrated circuits provides facilities for extracting design and layout information from digital image-mosaics captured during deconstruction of an integrated circuit. The design analysis workstation enables propagation of signal information from an annotation object having a signal property to at least one connected annotation object in order to point to errors in the design analysis.Type: GrantFiled: December 12, 2005Date of Patent: March 24, 2009Assignee: Chipworks Inc.Inventors: David F. Skoll, Terry Ludlow, Julia Elvidge
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Publication number: 20060095884Abstract: A design analysis workstation for performing design analysis of integrated circuits provides facilities for extracting design and layout information from digital image-mosaics captured during deconstruction of an integrated circuit. The design analysis workstation enables propagation of signal information from an annotation object having a signal property to at least one connected annotation object in order to point to errors in the design analysis.Type: ApplicationFiled: December 12, 2005Publication date: May 4, 2006Applicant: CHIPWORKSInventors: David Skoll, Terry Ludlow, Julia Elvidge
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Patent number: 7020853Abstract: A design analysis workstation for performing design analysis of integrated circuits provides facilities for extracting design and layout information from digital image-mosaics captured during deconstruction of an integrated circuit. Each image-mosaic is displayed in at least one mosaic-view as a background image that is overlaid with at least one annotation overlay. An engineer analyst creates annotation objects on the annotation overlay based on information inferred concurrently from one or more image-mosaics. Concurrent display of a plurality of image-mosaics facilitates the understanding of interrelations between components on different layers. The design analysis workstation displays a plurality of cursors in respective views of mosaic-images, the cursors having lock-step motion to facilitate comprehension of the alignment of features on different concurrently displayed image-mosaics.Type: GrantFiled: November 21, 2003Date of Patent: March 28, 2006Assignee: ChipworksInventors: David F. Skoll, Terry Ludlow, Julia Elvidge
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Publication number: 20040117750Abstract: A design analysis workstation for performing design analysis of integrated circuits provides facilities for extracting design and layout information from digital image-mosaics captured during deconstruction of an integrated circuit. Each image-mosaic is displayed in at least one mosaic-view as a background image that is overlaid with at least one annotation overlay. An engineer analyst creates annotation objects on the annotation overlay based on information inferred concurrently from one or more image-mosaics. Concurrent display of a plurality of image-mosaics facilitates the understanding of interrelations between components on different layers. The design analysis workstation displays a plurality of cursors in respective views of mosaic-images, the cursors having lock-step motion to facilitate comprehension of the alignment of features on different concurrently displayed image-mosaics.Type: ApplicationFiled: November 21, 2003Publication date: June 17, 2004Applicant: CHIPWORKSInventors: David F. Skoll, Terry Ludlow, Julia Elvidge
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Patent number: 6684379Abstract: A design analysis workstation for performing design analysis of integrated circuits provides facilities for extracting design and layout information from digital image-mosaics captured during deconstruction of an integrated circuit. Each image-mosaic is displayed in at least one mosaic-view as a background image that is overlaid with at least one annotation overlay. An engineer analyst creates annotation objects on the annotation overlay based on information inferred concurrently from one or more image-mosaics. Concurrent display of a plurality of image-mosaics facilitates the understanding of interrelations between components on different layers. The design analysis workstation displays a plurality of cursors in respective views of mosaic-images, the cursors having lock-step motion to facilitate comprehension of the alignment of features on different concurrently displayed image-mosaics.Type: GrantFiled: August 13, 2001Date of Patent: January 27, 2004Assignee: ChipworksInventors: David F. Skoll, Terry Ludlow, Julia Elvidge, Michael Phaneuf
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Patent number: 6453063Abstract: A method of imaging an integrated circuit using a focused ion beam system is presented. According to the method an integrated circuit is imaged in plan-view using a focused ion beam system. Circuit information is then extracted absent processing. In another embodiment, a method and system for imaging an entire IC automatically without removing the IC from the imaging system and requiring minimal operator intervention is presented. The method employs a focused ion beam system to image an exposed layer of an integrated circuit and then to etch a portion of the exposed layer in situ. Imaging and etching are repeated until substantially the entire integrated circuit is imaged. A processor is used to assemble the layers into a three-dimensional topography of the integrated circuit. Because of known relationships between layers, the mosaicing is facilitated and the final topography is more reliable than those produced by currently known computer implemented methods.Type: GrantFiled: January 28, 1999Date of Patent: September 17, 2002Assignee: ChipworksInventors: Michael Phaneuf, Dick James, Julia Elvidge, Pierrette Breton, Terry Ludlow, David Skoll, Bryan Socransky, Louise Weaver, Ray Haythornthwaite
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Publication number: 20020046386Abstract: A design analysis workstation for performing design analysis of integrated circuits provides facilities for extracting design and layout information from digital image-mosaics captured during deconstruction of an integrated circuit. Each image-mosaic is displayed in at least one mosaic-view as a background image that is overlaid with at least one annotation overlay. An engineer analyst creates annotation objects on the annotation overlay based on information inferred concurrently from one or more image-mosaics. Concurrent display of a plurality of image-mosaics facilitates the understanding of interrelations between components on different layers. The design analysis workstation displays a plurality of cursors in respective views of mosaic-images, the cursors having lock-step motion to facilitate comprehension of the alignment of features on different concurrently displayed image-mosaics.Type: ApplicationFiled: August 13, 2001Publication date: April 18, 2002Applicant: ChipworksInventors: David F. Skoll, Terry Ludlow, Julia Elvidge, Michael Phaneuf
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Patent number: 6288393Abstract: A method of analysing integrated circuits is provided. The method provides for scanning the integrated circuit with a beam in order to image an upper layer of the integrated circuit and performing chemical analysis on the upper layer of the integrated circuit. The chemical information and the imaging information are correlated and used to reverse engineer the integrated circuit.Type: GrantFiled: January 28, 1999Date of Patent: September 11, 2001Assignee: ChipworksInventors: Michael Phaneuf, Dick James, Pierrette Breton, Julia Elvidge, Ray Haythornthwaite