Abstract: A data communication interface has a delay-locked loop configured to generate a receive clock signal based on timing information provided by a signal received over a clock channel of a data communication link, a phase interpolator configured to provide a phase-shifted clock signal by phase-shifting one or more edges in the receive clock signal based on timing of transitions in a data signal received over a data channel of the data communication link, a clock and data recovery circuit configured to capture data from the data signal using the phase-shifted clock signal, and a calibration circuit. The calibration circuit is configured to calibrate the delay-locked loop while the clock and data recovery circuit is in an idle state, recalibrate the delay-locked loop when the clock and data recovery circuit is activated, and calibrate the clock and data recovery circuit after recalibrating the delay-locked loop.

Abstract: A phase locked loop (PLL) method includes generating a first signal based on a comparison of a phase of a reference clock or signal to a phase of a feedback clock; generating an output clock based on the first signal; generating an intermediate feedback clock including frequency dividing the output clock; fractionally frequency dividing the intermediate feedback clock based on a digital control signal to generate the feedback clock; and generating the digital control signal based on a sampling clock having a frequency greater than a frequency of the feedback clock. In one implementation, a PLL includes a frequency multiplier to generate the sampling clock based on the feedback clock. In another implementation, a PLL uses the intermediate feedback clock as the sampling clock.

Abstract: A phase locked loop (PLL) method includes generating a first signal based on a comparison of a phase of a reference clock or signal to a phase of a feedback clock; generating an output clock based on the first signal; generating an intermediate feedback clock including frequency dividing the output clock; fractionally frequency dividing the intermediate feedback clock based on a digital control signal to generate the feedback clock; and generating the digital control signal based on a sampling clock having a frequency greater than a frequency of the feedback clock. In one implementation, a PLL includes a frequency multiplier to generate the sampling clock based on the feedback clock. In another implementation, a PLL uses the intermediate feedback clock as the sampling clock.

Abstract: A method for fixing a dead-zone in a clock and data recovery (CDR) circuit is disclosed herein. The CDR circuit includes a CDR block and a phase interpolator, the CDR block is configured to generate phase codes based on signals from a phase detector, and the phase interpolator is configured to adjust a phase of a clock signal based on the phase codes. The method includes waiting for the CDR circuit to lock, reading a first phase code from the CDR block, changing the first phase code by a first amount to obtain a second phase code, and inputting the second phase code to the phase interpolator.

Abstract: A method for fixing a dead-zone in a clock and data recovery (CDR) circuit is disclosed herein. The CDR circuit includes a CDR block and a phase interpolator, the CDR block is configured to generate phase codes based on signals from a phase detector, and the phase interpolator is configured to adjust a phase of a clock signal based on the phase codes. The method includes waiting for the CDR circuit to lock, reading a first phase code from the CDR block, changing the first phase code by a first amount to obtain a second phase code, and inputting the second phase code to the phase interpolator.