Abstract: An SCR provides for increased holding voltage by decoupling the pnp and npn parasitic bipolar transistors of the SCR. In one embodiment, a N+ region is placed between the n+ region and the p+ region normally associated with conventional SCR devices, to formulate a new resistance. The new resistance is manifested to allow more current to flow through the new resistance rather than through the SCR parasitic pnp bipolar transistor. Since the parasitic pnp bipolar transistor no longer turns on as strongly as it would otherwise without the low resistance path through the new resistor, the holding voltage of the SCR is raised.

Abstract: A novel PNP driven NMOS (PDNMOS) protection scheme is provided for advanced nonsilicide/silicide submicron CMOS processes. The emitter of a PNP transistor and the drain of protection NMOS device are connected to an I/O pad for which ESD protection is provided by the PDNMOS. The collector of the PNP transistor and the gate of the protection NMOS transistor are connected to ground through a resistor. The source of the protection NMOS transistor is grounded. The base of the PNP transistor is connected to either a capacitor or the parasitic capacitor of the integrated circuit.

Abstract: An ESD protection structure which includes, preferably a single semiconductor chip, a forward SCR for coupling across a source of potential and a reverse SCR for coupling across the same source of potential which is non-symmetrical to the forward SCR. The breakdown voltage of the forward SCR is different from the breakdown voltage of the reverse SCR. Each of the SCRs has a separate triggering mechanism. None of the anode, cathode and triggering elements of the forward SCR are common to the reverse SCR. A unidirectional device, preferably a Schottky diode, is disposed in the body of semiconductor material between the forward and reverse SCRs to prevent conduction from the body of semiconductor material when the source of potential across the SCRs is reversed.