Patents by Inventor Julie ROLLINS
Julie ROLLINS has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11991873Abstract: Embodiments herein describe techniques for a semiconductor device including a substrate, a first inter-level dielectric (ILD) layer above the substrate, and a second ILD layer above the first ILD layer. A first capacitor and a second capacitor are formed within the first ILD layer and the second ILD layer. A first top plate of the first capacitor and a second top plate of the second capacitor are formed at a boundary between the first ILD layer and the second ILD layer. The first capacitor and the second capacitor are separated by a dielectric area in the first ILD layer. The dielectric area includes a first dielectric area that is coplanar with the first top plate or the second top plate, and a second dielectric area above the first dielectric area and to separate the first top plate and the second top plate. Other embodiments may be described and/or claimed.Type: GrantFiled: February 14, 2023Date of Patent: May 21, 2024Assignee: Intel CorporationInventors: Travis W. Lajoie, Abhishek A. Sharma, Van H. Le, Chieh-Jen Ku, Pei-Hua Wang, Jack T. Kavalieros, Bernhard Sell, Tahir Ghani, Gregory George, Akash Garg, Julie Rollins, Allen B. Gardiner, Shem Ogadhoh, Juan G. Alzate Vinasco, Umut Arslan, Fatih Hamzaoglu, Nikhil Mehta, Yu-Wen Huang, Shu Zhou
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Publication number: 20230200043Abstract: Embodiments herein describe techniques for a semiconductor device including a substrate, a first inter-level dielectric (ILD) layer above the substrate, and a second ILD layer above the first ILD layer. A first capacitor and a second capacitor are formed within the first ILD layer and the second ILD layer. A first top plate of the first capacitor and a second top plate of the second capacitor are formed at a boundary between the first ILD layer and the second ILD layer. The first capacitor and the second capacitor are separated by a dielectric area in the first ILD layer. The dielectric area includes a first dielectric area that is coplanar with the first top plate or the second top plate, and a second dielectric area above the first dielectric area and to separate the first top plate and the second top plate. Other embodiments may be described and/or claimed.Type: ApplicationFiled: February 14, 2023Publication date: June 22, 2023Inventors: Travis W. LAJOIE, Abhishek A. SHARMA, Van H. LE, Chieh-Jen KU, Pei-Hua WANG, Jack T. KAVALIEROS, Bernhard SELL, Tahir GHANI, Gregory GEORGE, Akash GARG, Julie ROLLINS, Allen B. GARDINER, Shem OGADHOH, Juan G. ALZATE VINASCO, Umut ARSLAN, Fatih HAMZAOGLU, Nikhil MEHTA, Yu-Wen HUANG, Shu ZHOU
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Publication number: 20230181421Abstract: A method for withdrawing a solution comprising a plurality of particles from a vial is disclosed. The method includes agitating the vial at a first predetermined mixing speed to suspend the plurality of particles in the solution. The method also includes withdrawing, during the agitating, a first volume of the solution from the vial with a pipette, such that an end of a pipette tip is positioned at a first predetermined depth within the vial.Type: ApplicationFiled: December 9, 2022Publication date: June 15, 2023Inventors: Jason Cyr, Kevin Chamberland, Stephan Hersey, Arvind Dev, Julie Rollins, Andrey Asanov
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Publication number: 20230182143Abstract: A device comprising a base and a support structure is disclosed. The base includes a vial receptacle for holding a vial. The support structure is coupled to an upper portion of the base and is configured to align a pipette comprising a pipette tip vertically over the vial receptacle. The support structure is configured to support a pipette such that an end of a pipette tip is positioned one or more predetermined depths within a vial in the vial receptacle.Type: ApplicationFiled: December 9, 2022Publication date: June 15, 2023Inventors: Kevin Chamberland, Jennifer Cote, Regina Lee Reif, Michael Thorpe, Jennifer Curtis, Arvind Dev, Julie Rollins, Andrey Asanov
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Publication number: 20230184636Abstract: A method for preparing an aliquot of solution comprising a plurality of particles is disclosed. The method includes agitating the solution with a baffle at a predetermined mixing speed to suspend the plurality of particles in the solution, wherein the baffle positioned at least partially within a vessel containing the solution, and wherein the vessel is engaged with a vessel receptacle configured to hold the vessel. The method also includes withdrawing, during the agitating, the aliquot of solution from the vessel with a pipette, such that an end of a pipette tip is positioned within the vessel.Type: ApplicationFiled: December 9, 2022Publication date: June 15, 2023Inventors: Arvind Dev, Julie Rollins, Richard Holt, Michael A. Schrameyer, Richard Lemieux, Nicholas Gustafson, Andrey Asanov
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Publication number: 20230184754Abstract: A method for preparing for preparing a solution comprising a plurality of particles in a vial is disclosed. The method includes agitating the vial at a first predetermined mixing speed. The method also includes dispersing, into the vial, during the agitating, a first volume of buffer solution at a first predetermined dispensing rate to suspend the plurality of particles in the solution, wherein particles of the plurality of particles comprise a unique identifying feature.Type: ApplicationFiled: December 9, 2022Publication date: June 15, 2023Inventors: Jason Cyr, Kevin Chamberland, Jennifer Cote, Arvind Dev, Julie Rollins, Andrey Asanov
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Patent number: 11652047Abstract: Embodiments herein describe techniques for a semiconductor device having an interconnect structure including an inter-level dielectric (ILD) layer between a first layer and a second layer of the interconnect structure. The interconnect structure further includes a separation layer within the ILD layer. The ILD layer includes a first area with a first height to extend from a first surface of the ILD layer to a second surface of the ILD layer. The ILD layer further includes a second area with a second height to extend from the first surface of the ILD layer to a surface of the separation layer, where the first height is larger than the second height. Other embodiments may be described and/or claimed.Type: GrantFiled: June 28, 2019Date of Patent: May 16, 2023Assignee: Intel CorporationInventors: Travis W. Lajoie, Abhishek A. Sharma, Van H. Le, Chieh-Jen Ku, Pei-Hua Wang, Jack T. Kavalieros, Bernhard Sell, Tahir Ghani, Gregory George, Akash Garg, Julie Rollins, Allen B. Gardiner, Shem Ogadhoh, Juan G. Alzate Vinasco, Umut Arslan, Fatih Hamzaoglu, Nikhil Mehta, Ting Chen, Vinaykumar V. Hadagali
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Patent number: 11610894Abstract: Embodiments herein describe techniques for a semiconductor device including a substrate, a first inter-level dielectric (ILD) layer above the substrate, and a second ILD layer above the first ILD layer. A first capacitor and a second capacitor are formed within the first ILD layer and the second ILD layer. A first top plate of the first capacitor and a second top plate of the second capacitor are formed at a boundary between the first ILD layer and the second ILD layer. The first capacitor and the second capacitor are separated by a dielectric area in the first ILD layer. The dielectric area includes a first dielectric area that is coplanar with the first top plate or the second top plate, and a second dielectric area above the first dielectric area and to separate the first top plate and the second top plate. Other embodiments may be described and/or claimed.Type: GrantFiled: June 28, 2019Date of Patent: March 21, 2023Assignee: Intel CorporationInventors: Travis W. Lajoie, Abhishek A. Sharma, Van H. Le, Chieh-Jen Ku, Pei-Hua Wang, Jack T. Kavalieros, Bernhard Sell, Tahir Ghani, Gregory George, Akash Garg, Julie Rollins, Allen B. Gardiner, Shem Ogadhoh, Juan G. Alzate Vinasco, Umut Arslan, Fatih Hamzaoglu, Nikhil Mehta, Yu-Wen Huang, Shu Zhou
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Publication number: 20200411426Abstract: Embodiments herein describe techniques for a semiconductor device having an interconnect structure including an inter-level dielectric (ILD) layer between a first layer and a second layer of the interconnect structure. The interconnect structure further includes a separation layer within the ILD layer. The ILD layer includes a first area with a first height to extend from a first surface of the ILD layer to a second surface of the ILD layer. The ILD layer further includes a second area with a second height to extend from the first surface of the ILD layer to a surface of the separation layer, where the first height is larger than the second height. Other embodiments may be described and/or claimed.Type: ApplicationFiled: June 28, 2019Publication date: December 31, 2020Inventors: Travis W. LAJOIE, Abhishek A. SHARMA, Van H. LE, Chieh-Jen KU, Pei-Hua WANG, Jack T. KAVALIEROS, Bernhard SELL, Tahir GHANI, Gregory GEORGE, Akash GARG, Julie ROLLINS, Allen B. GARDINER, Shem OGADHOH, Juan G. ALZATE VINASCO, Umut ARSLAN, Fatih HAMZAOGLU, Nikhil MEHTA, Ting CHEN, Vinaykumar V. HADAGALI
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Publication number: 20200411520Abstract: Embodiments herein describe techniques for a semiconductor device including a substrate, a first inter-level dielectric (ILD) layer above the substrate, and a second ILD layer above the first ILD layer. A first capacitor and a second capacitor are formed within the first ILD layer and the second ILD layer. A first top plate of the first capacitor and a second top plate of the second capacitor are formed at a boundary between the first ILD layer and the second ILD layer. The first capacitor and the second capacitor are separated by a dielectric area in the first ILD layer. The dielectric area includes a first dielectric area that is coplanar with the first top plate or the second top plate, and a second dielectric area above the first dielectric area and to separate the first top plate and the second top plate. Other embodiments may be described and/or claimed.Type: ApplicationFiled: June 28, 2019Publication date: December 31, 2020Inventors: Travis W. LAJOIE, Abhishek A. SHARMA, Van H. LE, Chieh-Jen KU, Pei-Hua WANG, Jack T. KAVALIEROS, Bernhard SELL, Tahir GHANI, Gregory GEORGE, Akash GARG, Julie ROLLINS, Allen B. GARDINER, Shem OGADHOH, Juan G. ALZATE VINASCO, Umut ARSLAN, Fatih HAMZAOGLU, Nikhil MEHTA, Yu-Wen HUANG, Shu ZHOU