Abstract: A method for determining fault sources for device failures comprises: generating failure signatures of fault sources for preselected tests; generating aggregate failure signatures for individual of the fault sources from the failure signatures; generating aggregate device test data from test data of a device for the preselected tests; generating aggregate matches by comparing the aggregate failure signatures with the aggregate device test data; and determining fault sources for device failures by comparing the test data of the device with ones of the failure signatures of fault sources corresponding to the aggregate matches. An apparatus configured to perform the method comprises at least one circuit.

Abstract: A method for eliminating false failures saved by redundant paths during critical area analysis of an integrated circuit layout is described. Monte Carlo simulation generates simulated defects for an integrated circuit layout. Vertices significantly encroached by the simulated defects are identified. Information of predefined sets of vertices associated with individual nets including at least one of the identified vertices is retrieved. Failures resulting from the simulated defects are indicated only if all elements of at least one of the predefined sets of vertices are one of the identified vertices. The predefined sets of vertices are determined prior to circuit area analysis by extracting nets from an integrated circuit layout, and determining the predefined sets of vertices for individual nets such that the net fails only if all elements of individual of the predefined sets of vertices are significantly encroached by simulated defects.

Abstract: A method for avoiding false failures attributable to dummy interconnects during defect analysis of an integrated circuit design is described. Described processing includes retrieving conductivity layers information for an integrated circuit design from a GDSII formatted file; defining a dummy polygons layer and a target layer; restoring interconnect polygons from the conductivity layers information into the dummy polygons layer; copying the interconnect polygons from the dummy polygons layer to the target layer, except for dummy interconnect polygons; and performing defect analysis of the integrated circuit design using the target layer.

Abstract: A method for determining between at least three origins of a coordinate system used for at least three different defect inspection spaces. The method comprises: collecting multiple sets of data spanning defect inspection spaces; filtering the data sets to remove points that introduce noise into correlation calculations; determining whether different data sets show correlation; selecting pairs of data sets showing correlation greater than or equal to a metric; and calculating coordinate offsets of at least three origins based on the selected pairs of data sets.

Abstract: A method for determining the number of redundancy units to employ in a memory integrated circuit. The critical areas for faults on each process layer in the integrated circuit for a range of defect sizes, and the signatures of the electrical responses of faulted circuits to input test stimuli are determined. A statistical frequency distribution for both the signatures for a ratio of defect sizes on each of the process layers, and for the occurrences of selected combinations of the signatures are determined. A ratio of the signature distribution for different numbers of redundancy units, and the die area for each of the different numbers of redundancy units are determined. The number of usable die per wafer is determined from the signature distribution and the die area. A level of redundancy that maximizes the number of usable die per wafer is selected.

Abstract: A method for determining the integrated circuit manufacturing operations that are the principle contributors to defect limited test yield loss comprises extracting the electrical faults for the important range of defect sizes from the layout data base; determining the signatures of the electrical response of faulted circuits to the input test stimuli; determining the statistical frequency distribution of the signatures for a fixed ratio of defect densities on the several process layers; determining the frequency distribution of the signatures observed in testing a wafer or group of wafers; and adjusting the defect densities amongst the process layers to minimize the difference between the predicted and observed frequency distributions such that the adjusted defect distribution provides a measure of the relative contribution of the process layers to yield loss.

Abstract: A method for eliminating false failures saved by redundant paths during critical area analysis of an integrated circuit layout is described. Monte Carlo simulation generates simulated defects for an integrated circuit layout. Vertices significantly encroached by the simulated defects are identified. Information of predefined sets of vertices associated with individual nets including at least one of the identified vertices is retrieved. Failures resulting from the simulated defects are indicated only if all elements of at least one of the predefined sets of vertices are one of the identified vertices. The predefined sets of vertices are determined prior to circuit area analysis by extracting nets from an integrated circuit layout, and determining the predefined sets of vertices for individual nets such that the net fails only if all elements of individual of the predefined sets of vertices are significantly encroached by simulated defects.

Abstract: A method for avoiding false failures attributable to dummy interconnects during defect analysis of an integrated circuit design is described. Described processing includes retrieving conductivity layers information for an integrated circuit design from a GDSII formatted file; defining a dummy polygons layer and a target layer; restoring interconnect polygons from the conductivity layers information into the dummy polygons layer; copying the interconnect polygons from the dummy polygons layer to the target layer, except for dummy interconnect polygons; and performing defect analysis of the integrated circuit design using the target layer.

Abstract: A method for determining the offset between at least three origins of a coordinate system used for at least three different defect inspection spaces. The method comprises: collecting multiple sets of data spanning defect inspection spaces; filtering the data sets to remove points that introduce noise into correlation calculations; determining whether different data sets show correlation; selecting pairs of data sets showing correlation greater than or equal to a metric; and calculating coordinate offsets of the at least three origins based on the said selected pairs of said data sets.

Abstract: A method for determining fault sources for device failures comprises: generating failure signatures of fault sources for preselected tests; generating aggregate failure signatures for individual of the fault sources from the failure signatures; generating aggregate device test data from test data of a device for the preselected tests; generating aggregate matches by comparing the aggregate failure signatures with the aggregate device test data; and determining fault sources for device failures by comparing the test data of the device with ones of the failure signatures of fault sources corresponding to the aggregate matches. An apparatus configured to perform the method comprises at least one circuit.