Patents by Inventor Julie Zhivich
Julie Zhivich has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240143523Abstract: One or more aspects of the present disclosure relate to controlling threads across several processors. For example, at least one input/output (IO) workflow message can be stored in a storage array's hardware queue. Additionally, an IO workflow message can be read from the hardware queue. Further, a local thread wake-up or an interrupt-wakeup operation can be performed based on a target of the IO workflow message.Type: ApplicationFiled: October 27, 2022Publication date: May 2, 2024Applicant: Dell Products L.P.Inventors: Troy Downing, Jonathan Krasner, Julie Zhivich
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Patent number: 11972112Abstract: A host IO devices directly implements host read operations on both local memory, and on peer memory via a PCIe non-transparent bridge. When a host read operation is received by a host IO device from a host, the host IO device uses an API to obtain the physical address of the requested data on the peer memory, and generates a PCIe Transaction Layer Packet (TLP) addressed to the address in the peer memory. The TLP addressed to an address in the peer memory is passed over the NTB to the peer compute node to retrieve the data stored in the addressed slot of peer memory. The requested data is returned to the host IO device over the NTB, stored in a buffer, and read out to the host to directy respond to the host read operation.Type: GrantFiled: January 27, 2023Date of Patent: April 30, 2024Assignee: Dell Products, L.P.Inventors: Jonathan Krasner, Ro Monserrat, Michael Scharland, Jerome Cartmell, James M Guyer, Scott Rowlands, Julie Zhivich, Thomas Mackintosh
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Patent number: 11784916Abstract: A control node and/or a storage processing node maybe configured to modify a control path between a control node and storage processing node to include at least a portion of a data fabric and another processing node. Control communications may be sent over the data fabric by encapsulating control information that is configured in accordance with a first technology of the control fabric within communications configured in accordance with a second technology of the data fabric. Control switching logic may include logic to switch to a modified control path that includes at least a portion of a data fabric: in response to a failure of the control path; to load balance management activity; and/or improve QoS of management activity.Type: GrantFiled: July 23, 2021Date of Patent: October 10, 2023Assignee: EMC IP Holding Company LLCInventors: Akash B. Appaiah, Julie Zhivich, Jason J. Duquette
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Publication number: 20230026171Abstract: A control node and/or a storage processing node maybe configured to modify a control path between a control node and storage processing node to include at least a portion of a data fabric and another processing node. Control communications may be sent over the data fabric by encapsulating control information that is configured in accordance with a first technology of the control fabric within communications configured in accordance with a second technology of the data fabric. Control switching logic may include logic to switch to a modified control path that includes at least a portion of a data fabric: in response to a failure of the control path; to load balance management activity; and/or improve QoS of management activity.Type: ApplicationFiled: July 23, 2021Publication date: January 26, 2023Applicant: EMC IP Holding Company LLCInventors: Akash B. Appaiah, Julie Zhivich, Jason J. Duquette
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Patent number: 11561698Abstract: A storage array that uses NVMEoF to interconnect compute nodes with NVME SSDs via a fabric and NVME offload engines implements flow control based on transaction latency. Transaction latency is the elapsed time between the send side completion message and receive side completion message for a single transaction. Counts of total transactions and over-latency-limit transactions are accumulated over a time interval. If the over limit rate exceeds a threshold, then the maximum allowed number of enqueued pending transactions is reduced. The maximum allowed number of enqueued pending transactions is periodically restored to a default value.Type: GrantFiled: April 20, 2021Date of Patent: January 24, 2023Assignee: EMC IP HOLDING COMPANY LLCInventors: Jinxian Xing, Julie Zhivich, John Krasner
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Publication number: 20220334727Abstract: A storage array that uses NVMEoF to interconnect compute nodes with NVME SSDs via a fabric and NVME offload engines implements flow control based on transaction latency. Transaction latency is the elapsed time between the send side completion message and receive side completion message for a single transaction. Counts of total transactions and over-latency-limit transactions are accumulated over a time interval. If the over limit rate exceeds a threshold, then the maximum allowed number of enqueued pending transactions is reduced. The maximum allowed number of enqueued pending transactions is periodically restored to a default value.Type: ApplicationFiled: April 20, 2021Publication date: October 20, 2022Applicant: EMC IP HOLDING COMPANY LLCInventors: Jinxian Xing, Julie Zhivich, John Krasner
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Publication number: 20210157487Abstract: A storage system includes four storage engines, each storage engine including two compute nodes. Eight point-to-point connections are used to interconnect pairs of compute nodes on different storage engines, such that each compute node is connected to exactly two other compute nodes of the storage system. Atomic operations can be initiated by any compute node on any other compute node. Atomic operations received by a compute node on one of the point-to-point connections will be forwarded on the other point-to-point connection if the atomic operation is not directed to the compute node. During normal operation, atomic operations on a given compute node are performed on a host adapter associated with the compute node. Upon failure of the host adapter associated with the compute node, atomic operations may be performed on the compute node using the host adapter of the other compute node of the storage engine.Type: ApplicationFiled: November 22, 2019Publication date: May 27, 2021Inventors: James Guyer, Jason Duquette, Alesia Tringale, Sean Pollard, Julie Zhivich, Jinxian Xian, William Baxter
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Patent number: 10853280Abstract: A storage system includes a storage engine having a first compute node, a second compute node, a first fabric adapter, and a second fabric adapter, the first compute node having a first memory and the second compute node having a second memory. The first compute node is connected to both the first and second fabric adapters, and the second compute node is connected to both the second and first fabric adapters. Both fabric adapters are configured to perform atomic operations on a memory of its respective compute node, and each fabric adapter contains a multi-initiating module configured to enable both the first compute node and the second compute node to initiate memory access operations on its respective memory.Type: GrantFiled: November 22, 2019Date of Patent: December 1, 2020Assignee: EMC IP Holding Company LLCInventors: James Guyer, Jason Duquette, Alesia Tringale, Julie Zhivich
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Patent number: 10652146Abstract: A method, computer program product, and computer system for identifying, by a computing device, a trigger event associated with an Ethernet switch. Ethernet based control information may be encapsulated into an InfiniBand based packet. The InfiniBand based packet with the Ethernet based control information may be transmitted over the InfiniBand fabric from a source to a destination. The Ethernet based control information may be decapsulated from the InfiniBand based packet at the destination.Type: GrantFiled: October 31, 2017Date of Patent: May 12, 2020Assignee: EMC IP Holding Company LLCInventors: Alesia A. Tringale, Abhinav Garg, Julie Zhivich, Adwait M. Sathe
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Patent number: 9952776Abstract: Storage node blades in a data storage system utilize queue pairs associated with point-to-point links to perform RDMA transactions with memory components associated with other storage node blades. Higher quality of service queue pairs are used for system message transactions and lower quality of service queue pairs are used for remote direct memory access data. Postings to a relatively higher priority queue pair are reduced when a corresponding relatively lower priority queue pair between the same pair of storage nodes via the same switch is starved of bandwidth. Postings to the relatively higher priority queue pair are increased when bandwidth starvation is remediated.Type: GrantFiled: July 24, 2015Date of Patent: April 24, 2018Assignee: EMC IP Holding Company LLCInventors: Alesia Tringale, Sean Pollard, Julie Zhivich, Jerome Cartmell
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Patent number: 9910753Abstract: A data storage system has first and second computing nodes that are interconnected by a switchless fabric. Each storage node includes first and second paired storage directors with an interconnecting communication link. Atomic operations sent between the computing nodes are mediated by network adapters. Atomic operations sent between paired storage directors via the interconnecting communication link are provided to a network adapter via an internal port and mediated by network adapter. The interconnecting communication links can be used as a backup path for atomic operations in the event of a link failure of the switchless fabric.Type: GrantFiled: December 18, 2015Date of Patent: March 6, 2018Assignee: EMC IP Holding Company LLCInventors: Alesia Tringale, Steven T. McClure, Jerome Cartmell, Julie Zhivich
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Patent number: 9753822Abstract: Individual transport connections within a dual-star fabric connected multi-node storage system are disabled in response to associated failures due to faulty hardware or temporal congestion. Each configured IB transport connection is monitored for viability and, upon failure, removed from the pool of available resource. Following failure restoration the resource is tested to ensure proper functionality and then restored to the pool of resources. Mappings associated with the transport connections are maintained while the connections are disabled.Type: GrantFiled: July 24, 2015Date of Patent: September 5, 2017Assignee: EMC IP HOLDING COMPANY LLCInventors: Alesia Tringale, Sean Pollard, Julie Zhivich