Patents by Inventor JULIEN LAMOUREUX
JULIEN LAMOUREUX has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11934825Abstract: A simulation system that includes a simulation accelerator that uses parallel processing to accelerate the simulation of register transfer level codes (RTLs) while minimizing memory access latency is disclosed. The accelerator has an array of parallel computing resources. The simulation accelerator receives compiled RTLs in which the components of the design are mapped to instructions. The instructions are divided into groups, in which instructions belonging to a same group are logically independent of each other. The simulation accelerator fetches instructions and data for processing by the parallel computing resources for one group of instructions at a time.Type: GrantFiled: February 28, 2022Date of Patent: March 19, 2024Assignee: Montana Systems Inc.Inventors: Vivian Chou, Julien Lamoureux, Sherman Lee
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Publication number: 20220197636Abstract: A simulation system that includes a simulation accelerator that uses parallel processing to accelerate the simulation of register transfer level codes (RTLs) while minimizing memory access latency is disclosed. The accelerator has an array of parallel computing resources. The simulation accelerator receives compiled RTLs in which the components of the design are mapped to instructions. The instructions are divided into groups, in which instructions belonging to a same group are logically independent of each other. The simulation accelerator fetches instructions and data for processing by the parallel computing resources for one group of instructions at a time.Type: ApplicationFiled: February 28, 2022Publication date: June 23, 2022Inventors: VIVIAN CHOU, JULIEN LAMOUREUX, SHERMAN LEE
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Patent number: 11275582Abstract: A simulation system that includes a simulation accelerator that uses parallel processing to accelerate the simulation of register transfer level codes (RTLs) while minimizing memory access latency is disclosed. The accelerator has an array of parallel computing resources. The simulation accelerator receives compiled RTLs in which the components of the design are mapped to instructions. The instructions are divided into groups, in which instructions belonging to a same group are logically independent of each other. The simulation accelerator fetches instructions and data for processing by the parallel computing resources for one group of instructions at a time.Type: GrantFiled: September 2, 2019Date of Patent: March 15, 2022Assignee: Montana Systems Inc.Inventors: Vivian Chou, Julien Lamoureux, Sherman Lee
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Publication number: 20190384598Abstract: A simulation system that includes a simulation accelerator that uses parallel processing to accelerate the simulation of register transfer level codes (RTLs) while minimizing memory access latency is disclosed. The accelerator has an array of parallel computing resources. The simulation accelerator receives compiled RTLs in which the components of the design are mapped to instructions. The instructions are divided into groups, in which instructions belonging to a same group are logically independent of each other. The simulation accelerator fetches instructions and data for processing by the parallel computing resources for one group of instructions at a time.Type: ApplicationFiled: September 2, 2019Publication date: December 19, 2019Inventors: VIVIAN CHOU, JULIEN LAMOUREUX, SHERMAN LEE
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Patent number: 10503504Abstract: A simulation system that includes a simulation accelerator that uses parallel processing to accelerate the simulation of register transfer level codes (RTLs) while minimizing memory access latency is disclosed. The accelerator has an array of parallel computing resources. The simulation accelerator receives compiled RTLs in which the components of the design are mapped to instructions. The instructions are divided into groups, in which instructions belonging to a same group are logically independent of each other. The simulation accelerator fetches instructions and data for processing by the parallel computing resources for one group of instructions at a time.Type: GrantFiled: January 6, 2017Date of Patent: December 10, 2019Assignee: Montana Systems Inc.Inventors: Vivian Chou, Julien Lamoureux, Sherman Lee
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Patent number: 10452393Abstract: A simulation system that includes a simulation accelerator that uses parallel processing to accelerate the simulation of register transfer level codes (RTLs) while minimizing memory access latency is disclosed. The accelerator has an array of parallel computing resources. The simulation accelerator receives compiled RTLs in which the components of the design are mapped to instructions. The instructions are divided into groups, in which instructions belonging to a same group are logically independent of each other. The simulation accelerator fetches instructions and data for processing by the parallel computing resources for one group of instructions at a time.Type: GrantFiled: January 6, 2017Date of Patent: October 22, 2019Assignee: Montana Systems Inc.Inventors: Vivian Chou, Julien Lamoureux, Sherman Lee
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Patent number: 10360028Abstract: A simulation system that includes a simulation accelerator that uses parallel processing to accelerate the simulation of register transfer level codes (RTLs) while minimizing memory access latency is disclosed. The accelerator has an array of parallel computing resources. The simulation accelerator receives compiled RTLs in which the components of the design are mapped to instructions. The instructions are divided into groups, in which instructions belonging to a same group are logically independent of each other. The simulation accelerator fetches instructions and data for processing by the parallel computing resources for one group of instructions at a time.Type: GrantFiled: January 6, 2017Date of Patent: July 23, 2019Assignee: Montana Systems Inc.Inventors: Vivian Chou, Julien Lamoureux, Sherman Lee
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Patent number: 10275244Abstract: A simulation system that includes a simulation accelerator that uses parallel processing to accelerate the simulation of register transfer level codes (RTLs) while minimizing memory access latency is disclosed. The accelerator has an array of parallel computing resources. The simulation accelerator receives compiled RTLs in which the components of the design are mapped to instructions. The instructions are divided into groups, in which instructions belonging to a same group are logically independent of each other. The simulation accelerator fetches instructions and data for processing by the parallel computing resources for one group of instructions at a time.Type: GrantFiled: January 6, 2017Date of Patent: April 30, 2019Assignee: Montana Systems Inc.Inventors: Vivian Chou, Julien Lamoureux, Sherman Lee
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Patent number: 10275245Abstract: A simulation system that includes a simulation accelerator that uses parallel processing to accelerate the simulation of register transfer level codes (RTLs) while minimizing memory access latency is disclosed. The accelerator has an array of parallel computing resources. The simulation accelerator receives compiled RTLs in which the components of the design are mapped to instructions. The instructions are divided into groups, in which instructions belonging to a same group are logically independent of each other. The simulation accelerator fetches instructions and data for processing by the parallel computing resources for one group of instructions at a time.Type: GrantFiled: January 6, 2017Date of Patent: April 30, 2019Assignee: Montana Systems Inc.Inventors: Vivian Chou, Julien Lamoureux, Sherman Lee
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Patent number: 10268478Abstract: A simulation system that includes a simulation accelerator that uses parallel processing to accelerate the simulation of register transfer level codes (RTLs) while minimizing memory access latency is disclosed. The accelerator has an array of parallel computing resources. The simulation accelerator receives compiled RTLs in which the components of the design are mapped to instructions. The instructions are divided into groups, in which instructions belonging to a same group are logically independent of each other. The simulation accelerator fetches instructions and data for processing by the parallel computing resources for one group of instructions at a time.Type: GrantFiled: January 6, 2017Date of Patent: April 23, 2019Assignee: Montana Systems Inc.Inventors: Vivian Chou, Julien Lamoureux, Sherman Lee
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Publication number: 20170255729Abstract: A simulation system that includes a simulation accelerator that uses parallel processing to accelerate the simulation of register transfer level codes (RTLs) while minimizing memory access latency is disclosed. The accelerator has an array of parallel computing resources. The simulation accelerator receives compiled RTLs in which the components of the design are mapped to instructions. The instructions are divided into groups, in which instructions belonging to a same group are logically independent of each other. The simulation accelerator fetches instructions and data for processing by the parallel computing resources for one group of instructions at a time.Type: ApplicationFiled: January 6, 2017Publication date: September 7, 2017Inventors: VIVIAN CHOU, JULIEN LAMOUREUX, SHERMAN LEE
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Publication number: 20170255466Abstract: A simulation system that includes a simulation accelerator that uses parallel processing to accelerate the simulation of register transfer level codes (RTLs) while minimizing memory access latency is disclosed. The accelerator has an array of parallel computing resources. The simulation accelerator receives compiled RTLs in which the components of the design are mapped to instructions. The instructions are divided into groups, in which instructions belonging to a same group are logically independent of each other. The simulation accelerator fetches instructions and data for processing by the parallel computing resources for one group of instructions at a time.Type: ApplicationFiled: January 6, 2017Publication date: September 7, 2017Inventors: VIVIAN CHOU, JULIEN LAMOUREUX, SHERMAN LEE
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Publication number: 20170255731Abstract: A simulation system that includes a simulation accelerator that uses parallel processing to accelerate the simulation of register transfer level codes (RTLs) while minimizing memory access latency is disclosed. The accelerator has an array of parallel computing resources. The simulation accelerator receives compiled RTLs in which the components of the design are mapped to instructions. The instructions are divided into groups, in which instructions belonging to a same group are logically independent of each other. The simulation accelerator fetches instructions and data for processing by the parallel computing resources for one group of instructions at a time.Type: ApplicationFiled: January 6, 2017Publication date: September 7, 2017Inventors: VIVIAN CHOU, JULIEN LAMOUREUX, SHERMAN LEE
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Publication number: 20170255730Abstract: A simulation system that includes a simulation accelerator that uses parallel processing to accelerate the simulation of register transfer level codes (RTLs) while minimizing memory access latency is disclosed. The accelerator has an array of parallel computing resources. The simulation accelerator receives compiled RTLs in which the components of the design are mapped to instructions. The instructions are divided into groups, in which instructions belonging to a same group are logically independent of each other. The simulation accelerator fetches instructions and data for processing by the parallel computing resources for one group of instructions at a time.Type: ApplicationFiled: January 6, 2017Publication date: September 7, 2017Inventors: VIVIAN CHOU, JULIEN LAMOUREUX, SHERMAN LEE
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Publication number: 20170255715Abstract: A simulation system that includes a simulation accelerator that uses parallel processing to accelerate the simulation of register transfer level codes (RTLs) while minimizing memory access latency is disclosed. The accelerator has an array of parallel computing resources. The simulation accelerator receives compiled RTLs in which the components of the design are mapped to instructions. The instructions are divided into groups, in which instructions belonging to a same group are logically independent of each other. The simulation accelerator fetches instructions and data for processing by the parallel computing resources for one group of instructions at a time.Type: ApplicationFiled: January 6, 2017Publication date: September 7, 2017Inventors: VIVIAN CHOU, JULIEN LAMOUREUX, SHERMAN LEE
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Publication number: 20170255716Abstract: A simulation system that includes a simulation accelerator that uses parallel processing to accelerate the simulation of register transfer level codes (RTLs) while minimizing memory access latency is disclosed. The accelerator has an array of parallel computing resources. The simulation accelerator receives compiled RTLs in which the components of the design are mapped to instructions. The instructions are divided into groups, in which instructions belonging to a same group are logically independent of each other. The simulation accelerator fetches instructions and data for processing by the parallel computing resources for one group of instructions at a time.Type: ApplicationFiled: January 6, 2017Publication date: September 7, 2017Inventors: VIVIAN CHOU, JULIEN LAMOUREUX, SHERMAN LEE