Patents by Inventor Julius Kovats
Julius Kovats has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11935824Abstract: An integrated circuit package module includes an integrated circuit package device including a contact element, and a bonding system formed on the integrated circuit package device. The bonding system includes a bonding system substrate and a bonding element formed in the bonding system substrate and conductively coupled to the contact element of the integrated circuit package device. The bonding element includes (a) a conduction component conductively connected to the contact element, the conduction component formed from a first metal having a first melting point, and (b) a bonding component formed from a second metal having a second melting point lower than the first melting point of the first metal.Type: GrantFiled: February 7, 2022Date of Patent: March 19, 2024Assignee: Microchip Technology IncorporatedInventors: Justin Sato, Bomy Chen, Yaojian Leng, Julius Kovats
-
Publication number: 20230290765Abstract: An apparatus having a substrate having first and second substrate contacts; a chip having a front-side chip contact and first and second back-side chip contacts, the front-side chip contact electrically connected to the first substrate contact; a chiplet having a chiplet contact electrically connected the first back-side chip contact; and a lead electrically connected to the second back-side chip contact and electrically connected to the second substrate contact.Type: ApplicationFiled: December 13, 2022Publication date: September 14, 2023Applicant: Microchip Technology IncorporatedInventors: Justin Sato, Bomy Chen, Julius Kovats, Anu Ramamurthy
-
Publication number: 20230260938Abstract: An integrated circuit device may include a multi-material toothed bond pad including (a) an array of vertically-extending teeth formed from a first material, e.g., aluminum, and (b) a fill material, e.g., silver, at least partially filling voids between the array of teeth. The teeth may be formed by depositing and etching aluminum or other suitable material, and the fill material may be deposited over the array of teeth and extending down into the voids between the teeth, and etched to expose top surfaces of the teeth. The array of teeth may collectively define an abrasive structure. The multi-material toothed bond pad may be bonded to another bond pad, e.g., using an ultrasonic or thermosonic bonding process, during which the abrasive teeth may abrade, break, or remove unwanted native oxide layers formed on the respective bond pad surfaces, to thereby create a direct and/or eutectic bonding between the bond pads.Type: ApplicationFiled: May 1, 2023Publication date: August 17, 2023Applicant: Microchip Technology IncorporatedInventors: Justin Sato, Bony Chen, Yaojian Leng, Gerald Marsico, Julius Kovats
-
Patent number: 11682641Abstract: An integrated circuit device may include a multi-material toothed bond pad including (a) an array of vertically-extending teeth formed from a first material, e.g., aluminum, and (b) a fill material, e.g., silver, at least partially filling voids between the array of teeth. The teeth may be formed by depositing and etching aluminum or other suitable material, and the fill material may be deposited over the array of teeth and extending down into the voids between the teeth, and etched to expose top surfaces of the teeth. The array of teeth may collectively define an abrasive structure. The multi-material toothed bond pad may be bonded to another bond pad, e.g., using an ultrasonic or thermosonic bonding process, during which the abrasive teeth may abrade, break, or remove unwanted native oxide layers formed on the respective bond pad surfaces, to thereby create a direct and/or eutectic bonding between the bond pads.Type: GrantFiled: February 1, 2021Date of Patent: June 20, 2023Assignee: Microchip Technology IncorporatedInventors: Justin Sato, Bomy Chen, Yaojian Leng, Gerald Marsico, Julius Kovats
-
Publication number: 20230109629Abstract: An electronic device includes a first interposer, a first integrated circuit (IC) device affixed to the first interposer, a second interposer, and a second IC device affixed to the second interposer. he second interposer is bonded to the first interposer. The first interposer includes first interposer circuitry and a first connection element electrically connected to the first interposer circuitry. The second interposer includes second interposer circuitry and a second connection element electrically connected to the second interposer circuitry. The second connection element is bonded to the first connection element to define a connection element pair. The connection element pair provides an electrical connection between the first interposer circuitry and the second interposer circuitry.Type: ApplicationFiled: February 8, 2022Publication date: April 6, 2023Applicant: Microchip Technology IncorporatedInventors: Justin Sato, Bomy Chen, Anu Ramamurthy, Julius Kovats
-
Publication number: 20230099856Abstract: An integrated circuit package module includes an integrated circuit package device including a contact element, and a bonding system formed on the integrated circuit package device. The bonding system includes a bonding system substrate and a bonding element formed in the bonding system substrate and conductively coupled to the contact element of the integrated circuit package device. The bonding element includes (a) a conduction component conductively connected to the contact element, the conduction component formed from a first metal having a first melting point, and (b) a bonding component formed from a second metal having a second melting point lower than the first melting point of the first metal.Type: ApplicationFiled: February 7, 2022Publication date: March 30, 2023Applicant: Microchip Technology IncorporatedInventors: Justin Sato, Bomy Chen, Yaojian Leng, Julius Kovats
-
Publication number: 20220052001Abstract: An integrated circuit device may include a multi-material toothed bond pad including (a) an array of vertically-extending teeth formed from a first material, e.g., aluminum, and (b) a fill material, e.g., silver, at least partially filling voids between the array of teeth. The teeth may be formed by depositing and etching aluminum or other suitable material, and the fill material may be deposited over the array of teeth and extending down into the voids between the teeth, and etched to expose top surfaces of the teeth. The array of teeth may collectively define an abrasive structure. The multi-material toothed bond pad may be bonded to another bond pad, e.g., using an ultrasonic or thermosonic bonding process, during which the abrasive teeth may abrade, break, or remove unwanted native oxide layers formed on the respective bond pad surfaces, to thereby create a direct and/or eutectic bonding between the bond pads.Type: ApplicationFiled: February 1, 2021Publication date: February 17, 2022Applicant: Microchip Technology IncorporatedInventors: Justin Sato, Bomy Chen, Yaojian Leng, Gerald Marsico, Julius Kovats
-
Publication number: 20080036098Abstract: A universal interconnect device for mounting and interconnecting a semiconductor integrated circuit die in preparation for mounting to another substrate such as a printed circuit board. The device consists of a laminate substrate having a first surface upon which the integrated circuit die may be mounted. Underlying and surrounding the die mount area is a plurality of substantially concentric electrically-conductive paths. Each of the plurality of paths is electrically isolated from each other and at least one of the plurality of electrically-conductive paths is located near an outer periphery of the laminate substrate. A plurality of vias traverse the laminate substrate a plurality of bonding features is mounted on a second surface of the substrate. Each of the bonding features is electrically isolated both from one another and from the plurality of paths but is electrically connectable to one or more of the paths through the plurality of vias.Type: ApplicationFiled: June 14, 2006Publication date: February 14, 2008Applicant: ATMEL CORPORATIONInventors: Julius A. Kovats, Kenneth M. Jackson
-
Patent number: 7271031Abstract: A device for electrically interconnecting one or more semiconductor devices to provide for flexibility in wiring and preventing long or shorted leads and methods for fabricating and using same. The device has a substrate with a plurality of substantially concentric electrically-conductive paths, each of the plurality of electrically-conductive paths being electrically isolated from each other and formed on a first surface of the substrate. At least one of the plurality of electrically-conductive paths is arranged concentrically so as to substantially span a width of the first surface of the substrate. A plurality of bonding pads is electrically coupled to each of the electrically-conductive paths. The plurality of bonding pads is coupled to one of the electrically-conductive paths and is electrically isolated from bonding pads located on any other electrically-conductive path. The entire interconnect device may be mounted in a standard leadframe product.Type: GrantFiled: May 30, 2006Date of Patent: September 18, 2007Assignee: Atmel CorporationInventors: Ken M. Lam, Julius A. Kovats
-
Publication number: 20060216866Abstract: A device for electrically interconnecting one or more semiconductor devices to provide for flexibility in wiring and preventing long or shorted leads and methods for fabricating and using same. The device has a substrate with a plurality of substantially concentric electrically-conductive paths, each of the plurality of electrically-conductive paths being electrically isolated from each other and formed on a first surface of the substrate. At least one of the plurality of electrically-conductive paths is arranged concentrically so as to substantially span a width of the first surface of the substrate. A plurality of bonding pads is electrically coupled to each of the electrically-conductive paths. The plurality of bonding pads is coupled to one of the electrically-conductive paths and is electrically isolated from bonding pads located on any other electrically-conductive path. The entire interconnect device may be mounted in a standard leadframe product.Type: ApplicationFiled: May 30, 2006Publication date: September 28, 2006Inventors: Ken Lam, Julius Kovats
-
Patent number: 7078792Abstract: A device for electrically interconnecting one or more semiconductor devices to provide for flexibility in wiring and preventing long or shorted leads and methods for fabricating and using same. The device has a substrate with a plurality of substantially concentric electrically-conductive paths, each of the plurality of electrically-conductive paths being electrically isolated from each other and formed on a first surface of the substrate. At least one of the plurality of electrically-conductive paths is arranged concentrically so as to substantially span a width of the first surface of the substrate. A plurality of bonding pads is electrically coupled to each of the electrically-conductive paths. The plurality of bonding pads is coupled to one of the electrically-conductive paths and is electrically isolated from bonding pads located on any other electrically-conductive path. The entire interconnect device may be mounted in a standard leadframe product.Type: GrantFiled: April 30, 2004Date of Patent: July 18, 2006Assignee: Atmel CorporationInventors: Ken M. Lam, Julius A. Kovats
-
Patent number: 6972486Abstract: The present invention allows non-wafer form devices to be tested on a standard automatic wafer-probe tester or other automated test or measurement device commonly employed in semiconductor or allied industries (e.g., flat panel display, data storage, or the like) processes. The present invention accomplishes this by providing a low-profile carrier for temporarily mounting a non-wafer form device. The low-profile carrier holds the non-wafer form device (e.g., an integrated circuit chip, a thin film head structure, one or more molded array packages, etc.) magnetically into recesses which are machined or otherwise formed in the low-profile carrier.Type: GrantFiled: September 12, 2003Date of Patent: December 6, 2005Assignee: Atmel CorporationInventors: Ken M. Lam, Julius A. Kovats
-
Publication number: 20050253278Abstract: A device for electrically interconnecting one or more semiconductor devices to provide for flexibility in wiring and preventing long or shorted leads and methods for fabricating and using same. The device has a substrate with a plurality of substantially concentric electrically-conductive paths, each of the plurality of electrically-conductive paths being electrically isolated from each other and formed on a first surface of the substrate. At least one of the plurality of electrically-conductive paths is arranged concentrically so as to substantially span a width of the first surface of the substrate. A plurality of bonding pads is electrically coupled to each of the electrically-conductive paths. The plurality of bonding pads is coupled to one of the electrically-conductive paths and is electrically isolated from bonding pads located on any other electrically-conductive path. The entire interconnect device may be mounted in a standard leadframe product.Type: ApplicationFiled: April 30, 2004Publication date: November 17, 2005Inventors: Ken Lam, Julius Kovats
-
Publication number: 20050060115Abstract: The present invention allows non-wafer form devices to be tested on a standard automatic wafer-probe tester or other automated test or measurement device commonly employed in semiconductor or allied industries (e.g., flat panel display, data storage, or the like) processes. The present invention accomplishes this by providing a low-profile carrier for temporarily mounting a non-wafer form device. The low-profile carrier holds the non-wafer form device (e.g., an integrated circuit chip, a thin film head structure, one or more molded array packages, etc.) magnetically into recesses which are machined or otherwise formed in the low-profile carrier.Type: ApplicationFiled: September 12, 2003Publication date: March 17, 2005Inventors: Ken Lam, Julius Kovats
-
Patent number: 6762117Abstract: A redistribution metallization scheme combines solder bumps and wire bond pads in addition to existing bond pads to enhance the connectivity of a semiconductor device, especially in flip-chip applications. The fabrication method includes forming the additional bond pads during the redistribution deposition step. The metals used in the redistribution layer provide a solderable surface for solder bumping and a bondable surface for wire bonding.Type: GrantFiled: January 27, 2003Date of Patent: July 13, 2004Assignee: Atmel CorporationInventors: Ken M. Lam, Julius A. Kovats
-
Publication number: 20030119297Abstract: A redistribution metallization scheme combines solder bumps and wire bond pads in addition to existing bond pads to enhance the connectivity of a semiconductor device, especially in flip-chip applications. The fabrication method includes forming the additional bond pads during the redistribution deposition step. The metals used in the redistribution layer provide a solderable surface for solder bumping and a bondable surface for wire bonding.Type: ApplicationFiled: January 27, 2003Publication date: June 26, 2003Inventors: Ken M. Lam, Julius A. Kovats
-
Patent number: 6577008Abstract: A redistribution metallization scheme combines solder bumps and wire bond pads in addition to existing bond pads to enhance the connectivity of a semiconductor device, especially in flip-chip applications. The fabrication method includes forming the additional bond pads during the redistribution deposition step. The metals used in the redistribution layer provide a solderable surface for solder bumping and a bondable surface for wire bonding.Type: GrantFiled: August 30, 2001Date of Patent: June 10, 2003Assignee: Atmel CorporationInventors: Ken M. Lam, Julius A. Kovats
-
Patent number: 6511901Abstract: A redistribution metallization scheme combines solder bumps and wire bond pads in addition to existing bond pads to enhance the connectivity of a semiconductor device, especially in flip-chip applications. The fabrication method includes forming the additional bond pads during the redistribution deposition step. The metals used in the redistribution layer provide a solderable surface for solder bumping and a bondable surface for wire bonding.Type: GrantFiled: November 5, 1999Date of Patent: January 28, 2003Assignee: Atmel CorporationInventors: Ken M. Lam, Julius A. Kovats
-
Patent number: 6376914Abstract: A diual-die integrated circuit package having two integrated circuit chips “flip chip” attached to each other and with one of the chips being aligned at a specified angle in relation to the other chip to allow access to bonding pads on the surface of each chip for wirebonding connection into the chip package. In a first embodiment, the two chips are rectangular in shape and are aligned at an angle of 90 degrees with respect to each other, thus allowing the end portions of the bottom chip to be accessible for connection into the chip package. Other embodiments maintain the chips at angles of less than 90 degrees, such that corner portions of each chip are accessible for connection into the chip package. The invention allows two identically constructed chips to be used for doubling or even greater multiplication of the functionality or memory of the IC package, while still using the same package footprint as for a single chip.Type: GrantFiled: December 9, 1999Date of Patent: April 23, 2002Assignee: Atmel CorporationInventors: Julius A. Kovats, Ken M. Lam
-
Publication number: 20020025585Abstract: A redistribution metallization scheme combines solder bumps and wire bond pads in addition to existing bond pads to enhance the connectivity of a semiconductor device, especially in flip-chip applications. The fabrication method includes forming the additional bond pads during the redistribution deposition step. The metals used in the redistribution layer provide a solderable surface for solder bumping and a bondable surface for wire bonding.Type: ApplicationFiled: August 30, 2001Publication date: February 28, 2002Inventors: Ken M. Lam, Julius A. Kovats