Abstract: A bias compensation self-aligned contact (SAC) etch endpoint detecting system is provided. The system includes an etch reactant chamber, an ESC power supply, and a signal processing computer. The etch reactant chamber includes an electrostatic chuck (ESC), a top electrode, and a bottom electrode. The ESC supports a substrate having an interlevel dielectric (ILD) layer to be etched. The ESC power supply is coupled to the ESC and is configured to function as a bias compensating power supply. The signal processing computer monitors a bias compensation signal generated by the ESC power supply. The etch process to be carried out in the etch reactant chamber is configured to be discontinued when the bias compensation signal is determined to have a previously ascertained characteristic evidencing an etch endpoint of the ILD layer.

Abstract: A method for enhancing the fabrication process of a self-aligned contact (SAC) structure is provided. The method includes forming a transistor structure on a surface of a substrate. The method also includes forming a dielectric layer directly over the surface of the substrate without forming an etch stop layer on the surface of the substrate. Also included in the method is plasma etching a contact hole through the dielectric layer in a plasma processing chamber. The method also includes monitoring a bias compensation voltage of the plasma processing chamber during the plasma etching process and discontinuing the plasma etching process upon detecting an endpoint signaling change in the bias compensation voltage.

Abstract: A method for enhancing the fabrication process of a self-aligned contact (SAC) structure is provided. The method includes forming a transistor structure on a surface of a substrate. The method also includes forming a dielectric layer directly over the surface of the substrate without forming an etch stop layer on the surface of the substrate. Also included in the method is plasma etching a contact hole through the dielectric layer in a plasma processing chamber. The method also includes monitoring a bias compensation voltage of the plasma processing chamber during the plasma etching process and discontinuing the plasma etching process upon detecting an endpoint signaling change in the bias compensation voltage.

Abstract: A method and structure are disclosed related to tapered contact holes in VLSI and ULSI technologies. The contact hole is formed by taking advantage of two-tiered polycide lines formed with a step. The polycide lines with steps are further formed with oxide spacers. The resulting structure is then used to form contact hole in between the oxide spacers. Because the oxide spacers are used—without the need for a tightly toleranced mask—to delimit the area of the contact at the bottom of the hole, a larger area of contact is obtained in addition to the tapered edges that are formed. Polycide is chosen to be a multilayer structure comprising tungsten-silicide (WSi2) over poly-silicon (poly-Si). Next, polycide is patterned by etching with a recipe which etches the WSi2 faster than it etches the underlying poly-Si. The etching, therefore, results in a structure where the WSi2 forms a step over the poly-Si layer.

Abstract: A method of forming a self-aligned contact in the fabrication of an integrated circuit is described. Semiconductor device structures are formed on a semiconductor substrate wherein their top and side surfaces are covered by a silicon nitride layer. A diagonal width of the silicon nitride layer on the side surfaces is a critical dimension. A layer of silicon oxide is deposited over the device structures and contacting the substrate adjacent to at least one of the semiconductor device structures where the self-aligned contact is to be formed. The substrate is covered with a layer of photoresist which is patterned to provide an opening over the planned self-aligned contact. Thereafter, the photoresist is exposed to ultraviolet light whereby the photoresist layer is cured.

Abstract: A method and structure are disclosed related to tapered contact holes in VLSI and ULSI technologies. The contact hole is formed by taking advantage of two-tiered polycide lines formed with a step. The polycide lines with steps are further formed with oxide spacers. The resulting structure is then used to form contact hole in between the oxide spacers. Because the oxide spacers are used--without the need for a tightly toleranced mask--to delimit the area of the contact at the bottom of the hole, a larger area of contact is obtained in addition to the tapered edges that are formed. Polycide is chosen to be a multilayer structure comprising tungsten-silicide (WSi.sub.2) over poly-silicon (poly-Si). Next, polycide is patterned by etching with a recipe which etches the WSi.sub.2 faster than it etches the underlying poly-Si. The etching, therefore, results in a structure where the WSi.sub.2 forms a step over the poly-Si layer.

Abstract: An anisotropic RIE procedure for creating a small diameter SAC opening, in an insulator layer, used in the fabrication sequence of a MOSFET device, and using a large area test site for RIE end point monitoring, has been developed. The RIE procedure features a RIE ambient, including oxygen as part of the RIE ambient, resulting in equal amounts of polymer deposition on the small diameter SAC opening, as well as on the large area test sites, during the reactive ion etching of the small diameter, SAC opening. This allows accurate monitoring of the RIE procedure to be performed on the large area test site, using optical ellipsometry procedures.

Abstract: A method for forming a via through a silicon oxide layer. There is first provided a substrate. There is then formed over the substrate a patterned silicon nitride layer which defines a contact beneath the patterned silicon nitride layer. There is then formed over the patterned silicon nitride layer a silicon oxide layer. There is then etched the silicon oxide layer through a first reactive ion etch (RIE) method employing a first etchant gas composition comprising a fluorocarbon etchant gas to form: (1) an etched silicon oxide layer which exposes the contact without substantially etching the patterned silicon nitride layer; and (2) a fluorocarbon polymer residue layer formed upon at least one of the etched silicon oxide layer and the patterned silicon nitride layer. Finally, there is stripped from the substrate the fluorocarbon polymer residue layer through a second reactive ion etch (RIE) method employing a second etchant gas composition comprising carbon tetrafluoride and oxygen.

Abstract: The present invention is a method for using a single SiN layer as a passivation film. The single layer SiN can be strengthened to withstand stress by adjusting the process parameters during formation of the SiN layer. In general, the process can be changed by increasing the low frequency power 5% during the deposition. Alternatively, the pressure of the SiN deposition may be decreased about 20% in pressure.