Patents by Inventor Jun Hirota
Jun Hirota has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20160377651Abstract: A measuring method of a scanning probe microscopy moves the probe from the first measuring point to the second measuring point while the probe has contact with the object to be measured and a pressing force weaker than the first pressing force is applied between the probe and the object to be measured after the measurement at the first measuring point has ended, applies the first pressing force between the probe and the object to be measured until the tip end position of the probe reaches the first distance in the depth direction from the upper surface of the object to be measured, and measures the physical property information of the object to be measured after the tip end position of the probe has reached the first distance in the depth direction from the upper surface of the object to be measured at the second measuring point.Type: ApplicationFiled: March 11, 2016Publication date: December 29, 2016Inventors: Jun HIROTA, Kazunori Harada, Tsukasa Nakai
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Patent number: 9410983Abstract: A scanning probe microscope includes a stage on which a sample is mounted, a probe configured to measure a characteristic of the sample, and a controller configured to move the probe and the stage relative to each other along a scanning trajectory during measurement of the characteristic of the sample. The scanning trajectory includes a plurality of linear segments, wherein each pair of adjacent linear segments form an angle that is 90 degrees or less.Type: GrantFiled: February 28, 2014Date of Patent: August 9, 2016Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Hideo Shinomiya, Jun Hirota, Kazunori Harada, Moto Yabuki
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Publication number: 20150059025Abstract: A scanning probe microscope includes a stage on which a sample is mounted, a probe configured to measure a characteristic of the sample, and a controller configured to move the probe and the stage relative to each other along a scanning trajectory during measurement of the characteristic of the sample. The scanning trajectory includes a plurality of linear segments, wherein each pair of adjacent linear segments form an angle that is 90 degrees or less.Type: ApplicationFiled: February 28, 2014Publication date: February 26, 2015Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Hideo SHINOMIYA, Jun HIROTA, Kazunori HARADA, Moto YABUKI
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Patent number: 8664631Abstract: According to one embodiment, a nonvolatile memory device includes a word line interconnect layer, a bit line interconnect layer, a pillar, and charge bearing members. The word line interconnect layer includes a plurality of word lines extending in a first direction. The bit line interconnect layer includes a plurality of bit lines extending in a second direction that intersects the first direction. The pillar is disposed between each of the word lines and each of the bit lines. The charge bearing members contain a negative fixed charge, and provided on side faces of the pillars. The pillars includes a diode film provided with a p-type layer and an n-type layer and a variable resistance film stacked on the diode film. The charge bearing member is disposed on side faces of the p-type layer, and is not disposed on side faces of the n-type layer.Type: GrantFiled: September 20, 2011Date of Patent: March 4, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Jun Hirota, Yoko Iwakaji, Moto Yabuki
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Patent number: 8558354Abstract: According to one embodiment, a semiconductor device includes a plurality of silicon films. The plurality of silicon films are disposed on one plane and are made of polysilicon containing an impurity. A crystal orientation of each of the silicon films is a (311) orientation.Type: GrantFiled: March 21, 2011Date of Patent: October 15, 2013Assignee: Kabushiki Kaisha ToshibaInventors: Yoko Iwakaji, Jun Hirota, Moto Yabuki, Wakana Kai, Hirokazu Ishida, Ichiro Mizushima
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Patent number: 8436331Abstract: According to one embodiment, a method for manufacturing a memory device is disclosed. The method includes forming a silicon diode. At least an upper portion of the silicon diode is made of a semiconductor material containing silicon and doped with impurity. The method includes forming a metal layer made of a metal on the silicon diode. The method includes forming a metal nitride layer made of a nitride of the metal on the metal layer. The method includes forming a resistance change film. In addition, the method includes reacting the metal layer with the silicon diode and the metal nitride layer by heat treatment to form an electrode film containing the metal, silicon, and nitrogen.Type: GrantFiled: July 27, 2010Date of Patent: May 7, 2013Assignee: Kabushiki Kaisha ToshibaInventors: Yoko Iwakaji, Jun Hirota, Kyoichi Suguro, Moto Yabuki
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Publication number: 20130077461Abstract: A storage device includes a recording medium, a probe, a substrate, and a processing unit. The recording medium stores a signal. The probe reads or writes the signal to/from the recording medium. The substrate is provided with the probe via a conductive anchor interposed therebetween and a first connection terminal connected to the probe. The processing unit is provided on the substrate and has a second connection terminal. The second connection terminal is connected to the first connection terminal.Type: ApplicationFiled: March 19, 2012Publication date: March 28, 2013Inventors: Akihiro Koga, Yasushi Tomizawa, Hideo Shinomiya, Moto Yabuki, Jun Hirota, Yoshihisa Iwata, Masayuki Ichige, Kikuko Sugimae, Junya Matsunami
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Patent number: 8309958Abstract: According to one embodiment, a semiconductor memory device includes a word line interconnection layer, a bit line interconnection layer and a pillar. The word line interconnection layer includes a plurality of word lines which extend in a first direction. The bit line interconnection layer includes a plurality of bit lines which extend in a second direction crossing over the first direction. The pillar is arranged between each of the word lines and each of the bit lines. The pillar includes a silicon diode and a variable resistance film, and the silicon diode includes a p-type portion and an n-type portion. The word line interconnection layer and the bit line interconnection layer are alternately stacked, and a compressive force is applied to the silicon diode in a direction in which the p-type portion and the n-type portion become closer to each other.Type: GrantFiled: August 31, 2010Date of Patent: November 13, 2012Assignee: Kabushiki Kaisha ToshibaInventors: Jun Hirota, Yoko Iwakaji, Moto Yabuki
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Publication number: 20120235107Abstract: According to one embodiment, a nonvolatile memory device includes a word line interconnect layer, a bit line interconnect layer, a pillar, and charge bearing members. The word line interconnect layer includes a plurality of word lines extending in a first direction. The bit line interconnect layer includes a plurality of bit lines extending in a second direction that intersects the first direction. The pillar is disposed between each of the word lines and each of the bit lines. The charge bearing members contain a negative fixed charge, and provided on side faces of the pillars. The pillars includes a diode film provided with a p-type layer and an n-type layer and a variable resistance film stacked on the diode film. The charge bearing member is disposed on side faces of the p-type layer, and is not disposed on side faces of the n-type layer.Type: ApplicationFiled: September 20, 2011Publication date: September 20, 2012Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Jun Hirota, Yoko Iwakaji, Moto Yabuki
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Publication number: 20120091414Abstract: According to one embodiment, a semiconductor device includes a plurality of silicon films. The plurality of silicon films are disposed on one plane and are made of polysilicon containing an impurity. A crystal orientation of each of the silicon films is a (311) orientation.Type: ApplicationFiled: March 21, 2011Publication date: April 19, 2012Applicant: Kabushiki Kaisha ToshibaInventors: Yoko IWAKAJI, Jun Hirota, Moto Yabuki, Wakana Kai, Hirokazu Ishida, Ichiro Mizushima
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Patent number: 8084830Abstract: The memory cell is located at respective intersections between the first wirings and the second wirings. Each of the memory cells has a rectifier element and a variable resistance element connected in series. The rectifier element includes a p type first semiconductor region, and a n type second semiconductor region. The first semiconductor region is formed of, at least in part, silicon-germanium mixture (Si1-xGex (0<x<=1)). The second semiconductor region is formed of silicon (Si).Type: GrantFiled: September 9, 2009Date of Patent: December 27, 2011Assignee: Kabushiki Kaisha ToshibaInventors: Hiroshi Kanno, Kenichi Murooka, Jun Hirota, Hideyuki Tabata
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Publication number: 20110233506Abstract: According to one embodiment, a nonvolatile memory device includes a first electrode, a second electrode, a resistance change portion and a select element. The resistance change portion is provided between the first electrode and the second electrode and configured to transition between a first resistance state and a second resistance state. The select element is provided between the resistance change portion and the first electrode and has a p-layer including a p-type semiconductor, an i-layer including an intrinsic semiconductor, and an n-layer including an n-type semiconductor. The select element contains an impurity having a smaller bandgap energy than the intrinsic semiconductor, and a concentration peak of the impurity in the i-layer is placed in a center portion of layer thickness of the i-layer.Type: ApplicationFiled: September 1, 2010Publication date: September 29, 2011Applicant: Kabushiki Kaisha ToshibaInventors: Yoko IWAKAJI, Jun HIROTA, Moto YABUKI
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Publication number: 20110227025Abstract: According to one embodiment, a semiconductor memory device includes a word line interconnection layer, a bit line interconnection layer and a pillar. The word line interconnection layer includes a plurality of word lines which extend in a first direction. The bit line interconnection layer includes a plurality of bit lines which extend in a second direction crossing over the first direction. The pillar is arranged between each of the word lines and each of the bit lines. The pillar includes a silicon diode and a variable resistance film, and the silicon diode includes a p-type portion and an n-type portion. The word line interconnection layer and the bit line interconnection layer are alternately stacked, and a compressive force is applied to the silicon diode in a direction in which the p-type portion and the n-type portion become closer to each other.Type: ApplicationFiled: August 31, 2010Publication date: September 22, 2011Applicant: Kabushiki Kaisha ToshibaInventors: Jun HIROTA, Yoko Iwakaji, Moto Yabuki
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Publication number: 20110193049Abstract: According to one embodiment, a method for manufacturing a memory device is disclosed. The method includes forming a silicon diode. At least an upper portion of the silicon diode is made of a semiconductor material containing silicon and doped with impurity. The method includes forming a metal layer made of a metal on the silicon diode. The method includes forming a metal nitride layer made of a nitride of the metal on the metal layer. The method includes forming a resistance change film. In addition, the method includes reacting the metal layer with the silicon diode and the metal nitride layer by heat treatment to form an electrode film containing the metal, silicon, and nitrogen.Type: ApplicationFiled: July 27, 2010Publication date: August 11, 2011Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Yoko IWAKAJI, Jun Hirota, Kyoichi Suguro, Moto Yabuki
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Publication number: 20100213550Abstract: The memory cell is located at respective intersections between the first wirings and the second wirings. Each of the memory cells has a rectifier element and a variable resistance element connected in series. The rectifier element includes a p type first semiconductor region, and a n type second semiconductor region. The first semiconductor region is formed of, at least in part, silicon-germanium mixture (Sii-xGex (0<x<=1)). The second semiconductor region is formed of silicon (Si).Type: ApplicationFiled: September 9, 2009Publication date: August 26, 2010Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Hiroshi Kanno, Kenichi Murooka, Jun Hirota, Hideyuki Tabata
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Patent number: 7759796Abstract: A semiconductor device according to an embodiment of the present invention includes a line layer containing Cu (copper), an inter layer dielectric formed on the line layer, a via hole formed in the inter layer dielectric on the line layer, a first barrier layer formed on the line layer in the via hole, a second barrier layer formed on the first barrier layer and on a sidewall of the via hole, and a conductive layer formed on the second barrier layer and containing Al (aluminum).Type: GrantFiled: May 23, 2008Date of Patent: July 20, 2010Assignee: Kabushiki Kaisha ToshibaInventor: Jun Hirota
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Patent number: 7521352Abstract: A method for manufacturing a semiconductor device includes forming a copper anti-diffusion film on a copper trench wiring layer, and forming an opening portion in the copper anti-diffusion film by laser ablation, the opening portion being formed in a region corresponding to an alignment region used for lithography process for forming an aluminum wiring on the copper trench wiring layer.Type: GrantFiled: April 27, 2007Date of Patent: April 21, 2009Assignee: Kabushiki Kaisha ToshibaInventors: Hideo Shinomiya, Jun Hirota, Mie Matsuo, Hisashi Kaneko
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Patent number: 7463297Abstract: To enable acquisition of image data in multiple tone levels in a short capturing time, a liquid crystal display device 1 includes a photodiode having sensitivity R, a capacitor having capacitance C and configured to store a charge in response to an electric signal converted by the photodiode in a state where an initial voltage V is applied thereto, a SRAM configured to retain binary data which indicate as to whether or not an amount of charge stored in the capacitor is equal to or above a threshold voltage Vth, an image capturing control unit 5 configured to generate pixel data in multiple tone levels based on the binary data outputted from the SRAM of a plurality of adjacent pixels. Here, at least any one value of R, V, C, and Vth in each of the pixels is set to a different value from relevant values of other adjacent pixels.Type: GrantFiled: November 30, 2004Date of Patent: December 9, 2008Assignee: Toshiba Matsushita Display Technology Co., Ltd.Inventors: Masahiro Yoshida, Takashi Nakamura, Hirotaka Hayashi, Norio Tada, Jun Hirota, Masaki Kinoshita
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Publication number: 20080296769Abstract: A semiconductor device according to an embodiment of the present invention includes a line layer containing Cu (copper), an inter layer dielectric formed on the line layer, a via hole formed in the inter layer dielectric on the line layer, a first barrier layer formed on the line layer in the via hole, a second barrier layer formed on the first barrier layer and on a sidewall of the via hole, and a conductive layer formed on the second barrier layer and containing Al (aluminum).Type: ApplicationFiled: May 23, 2008Publication date: December 4, 2008Inventor: Jun HIROTA
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Patent number: 7392058Abstract: A communication terminal device includes a first display part configured to display streaming sub information, a second display part configured to display streaming main information related to the streaming sub information, a sub information reception unit configured to receive the streaming sub information sequentially transmitted from an information providing device and to display the received streaming sub information on the first display part, a request transmission unit configured to transmit to the information providing device an information request signal for requesting the streaming main information related to the streaming sub information displayed on the first display part, and a main information reception unit configured to receive the streaming main information and to display the streaming main information on the second display part.Type: GrantFiled: May 2, 2005Date of Patent: June 24, 2008Assignee: Toshiba Matsushita Display Technology Co., Ltd.Inventors: Jun Hirota, Masaki Kinoshita