Abstract: A semiconductor device includes a stack structure including first electrodes and insulating layers alternately stacked on each other, a second electrode passing through the stack structure, and variable resistance patterns each interposed between the second electrode and a corresponding one of the first electrodes. Each of the first electrodes includes a first sidewall facing the second electrode, and each of the insulating layers includes a second sidewall facing the second electrode. At least a part of each of the variable resistance patterns protrudes farther towards the second electrode than the second sidewall.

Abstract: A sputtering target and a method for fabricating an electronic device using the same are provided. A sputtering target may include a carbon-doped GeSbTe alloy, wherein, for the carbon-doped GeSbTe alloy, an average grain diameter of a GeSbTe alloy after sintering is in a range of 0.5 ?m to 5 ?m, and a first ratio of an average grain diameter of carbon after the sintering is Y (?m) to the average grain diameter of the GeSbTe alloy after the sintering may be in a range of greater than 0.5 and equal to or less than 1.5. Alternatively, for the carbon-doped GeSbTe alloy, a condition of Y=X×(Z/100) may be satisfied, where an average grain diameter of a GeSbTe alloy after sintering is X (?m), an average grain diameter of carbon after the sintering is Y (?m), and a content of carbon is Z (at %).

Abstract: A semiconductor memory device includes a memory cell interposed between a first electrode and a second electrode, and configured with a chalcogenide layer that includes three or more components, and a peripheral circuit for providing the memory cell with a program pulse inducing a compositional gradient in the chalcogenide layer.

Abstract: A chalcogenide material may include germanium (Ge), arsenic (As), selenium (Se) and from 0.5 to 10 at % of at least one group 13 element. A variable resistance memory device may include a first electrode, a second electrode, and a chalcogenide film interposed between the first electrode and the second electrode and including from 0.5 to 10 at % of at least one group 13 element. In addition, an electronic device may include a semiconductor memory. The semiconductor memory may include a column line, a row line intersecting the column line, and a memory cell positioned between the column line and the row line, wherein the memory cell comprises a chalcogenide film including germanium (Ge), arsenic (As), selenium (Se), and from 0.5 to 10 at % of at least one group 13 element.

Abstract: An electronic device including a semiconductor memory is provided. The semiconductor memory includes a plurality of first lines extending in a first direction; a plurality of second lines over the first lines, the second lines extending in a second direction crossing the first direction; a plurality of memory cells disposed at intersection regions of the first lines and the second lines between the first lines and the second lines in a third direction perpendicular to the first and second directions; and a heat sink positioned between two memory cells adjacent to each other in a diagonal direction with respect to the first and second directions.

Abstract: A PVD chamber shield includes: a shield configured to surround a space between a sputtering target and a substrate that are disposed in a PVD chamber body, the shield having a hollow shape with an inner surface and an outer surface; and a coating layer formed over the inner surface of the shield. The coating layer has i) a dielectric constant not greater than a dielectric constant of a material deposited over the substrate, ii) a porosity greater than 0 vol % and less than 100 vol %, and iii) a thickness greater than 150 pm and less than a given upper limit, the upper limit being set to prevent an occurrence of peeling of a material deposited over the coating layer.

Abstract: A semiconductor device may include a first electrode, a second electrode, an insulating layer interposed between the first electrode and the second electrode and including an opening having an inclined sidewall, a variable resistance layer formed in the opening, and a liner interposed between the variable resistance layer and the insulating layer and between the variable resistance layer and the first electrode. The variable resistance layer includes a first surface and a second surface, the first surface facing the first electrode and having a first area, the second surface facing the second electrode and having a second area different from the first area. The variable resistance layer maintains an amorphous state during a program operation.

Abstract: A sputtering target and a method for fabricating an electronic device using the same are provided. A sputtering target may include a carbon-doped GeSbTe alloy, wherein, for the carbon-doped GeSbTe alloy, an average grain diameter of a GeSbTe alloy after sintering is in a range of 0.5 ?m to 5 ?m, and a first ratio of an average grain diameter of carbon after the sintering is Y (?m) to the average grain diameter of the GeSbTe alloy after the sintering may be in a range of greater than 0.5 and equal to or less than 1.5. Alternatively, for the carbon-doped GeSbTe alloy, a condition of Y=X×(Z/100) may be satisfied, where an average grain diameter of a GeSbTe alloy after sintering is X (?m), an average grain diameter of carbon after the sintering is Y (?m), and a content of carbon is Z (at %).

Abstract: A semiconductor device includes a stack structure including first electrodes and insulating layers alternately stacked on each other, a second electrode passing through the stack structure, and variable resistance patterns each interposed between the second electrode and a corresponding one of the first electrodes. Each of the first electrodes includes a first sidewall facing the second electrode, and each of the insulating layers includes a second sidewall facing the second electrode. At least a part of each of the variable resistance patterns protrudes farther towards the second electrode than the second sidewall.

Abstract: An electronic device including a semiconductor memory is provided. The semiconductor memory includes a plurality of first lines extending in a first direction; a plurality of second lines over the first lines, the second lines extending in a second direction crossing the first direction; a plurality of memory cells disposed at intersection regions of the first lines and the second lines between the first lines and the second lines in a third direction perpendicular to the first and second directions; and a heat sink positioned between two memory cells adjacent to each other in a diagonal direction with respect to the first and second directions.

Abstract: A sputtering target includes: a base configured to transfer heat in a basal plane direction; and a first heat sink disposed on a sidewall of the base, the first heat sink configured to transfer heat along a direction that is different from the basal plane direction.

Abstract: A chalcogenide material may include germanium (Ge), arsenic (As), selenium (Se) and from 0.5 to 10 at % of at least one group 3 element. A variable resistance memory device may include a first electrode, a second electrode, and a chalcogenide film interposed between the first electrode and the second electrode and including from 0.5 to 10 at % of at least one group 3 element. In addition, an electronic device may include a semiconductor memory. The semiconductor memory may include a column line, a row line intersecting the column line, and a memory cell positioned between the column line and the row line, wherein the memory cell comprises a chalcogenide film including germanium (Ge), arsenic (As), selenium (Se), and from 0.5 to 10 at % of at least one group 3 element.

Abstract: A sputtering target includes: a base configured to transfer heat in a basal plane direction; and a first heat sink disposed on a sidewall of the base, the first heat sink configured to transfer heat along a direction that is different from the basal plane direction.

Abstract: A method of forming a tungsten film including disposing a substrate inside a process chamber; performing a tungsten nucleation layer forming operation for forming a tungsten nucleation layer on the substrate, performing a first operation for forming a portion of a tungsten bulk layer on the tungsten nucleation layer by alternately supplying a tungsten-containing gas and a reducing gas into the process chamber, and performing a second operation for stopping the supply of the tungsten-containing gas and the reducing gas and removing a remaining gas in the process chamber may be provided. The first operation and the second operation may be repeated at least twice until the tungsten bulk layer reaches a desired thickness.

Abstract: In a method of manufacturing a phase change memory device, an insulating interlayer having a through opening is formed on a substrate, at least one conformal phase change material layer pattern is formed along the sides of the opening, and a plug-like phase change material pattern having a composition different from that of each conformal phase change material layer pattern is formed on the at least one conformal phase change material layer pattern as occupying a remaining portion of the opening. Energy is applied to the phase change material layer patterns to form a mixed phase change material layer pattern including elements from the conformal and plug-like phase change material layer patterns.

Abstract: In a method of manufacturing a phase change memory device, an insulating interlayer having a through opening is formed on a substrate, at least one conformal phase change material layer pattern is formed along the sides of the opening, and a plug-like phase change material pattern having a composition different from that of each conformal phase change material layer pattern is formed on the at least one conformal phase change material layer pattern as occupying a remaining portion of the opening. Energy is applied to the phase change material layer patterns to form a mixed phase change material layer pattern including elements from the conformal and plug-like phase change material layer patterns.

Abstract: Example methods of filling an opening and of manufacturing a phase change memory device are disclosed. In an example method, an insulation layer having an opening is formed on a substrate. A material layer is formed on the insulation layer. The material layer fills the opening, and has a void. A first laser beam is irradiated onto the material layer, thereby removing the void or reducing a size of the void. The first laser beam is generated from a solid state laser medium.

Abstract: Disclosed herein is a method for manufacturing (In)—(Sb)—(Te) (IST) nanowires and a phase-change memory device comprising the nanowires. The method comprises providing a substrate and vapors of In, Sb and Te precursors in a chamber and allowing the vapors to react with each other on the substrate in the chamber at a temperature of 230-300° C. and a pressure of 7-15 Torr. With the method, IST nanowires can be fabricated cost-effectively.

Abstract: Disclosed herein is a method for manufacturing (In)—(Sb)—(Te) (IST) nanowires and a phase-change memory device comprising the nanowires. The method comprises providing a substrate and vapors of In, Sb and Te precursors in a chamber and allowing the vapors to react with each other on the substrate in the chamber at a temperature of 230-300° C. and a pressure of 7-15 Torr. With the method, IST nanowires can be fabricated cost-effectively.