Patents by Inventor Jun-Lin Yeh

Jun-Lin Yeh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11682470
    Abstract: A memory device including a memory cell array, a redundant fuse circuit and a memory controller is provided. The memory cell array includes multiple regular memory blocks and multiple redundant memory blocks. The redundant fuse circuit includes multiple fuse groups recording multiple repair information. Each repair information is associated with a corresponding one of the redundant memory blocks and includes a repair address, a first enable bit, and a second enable bit. The memory controller includes multiple determining circuits. Each of the multiple determining circuits generates a hit signal according to an operation address, the repair address, the first enable bit, and the second enable bit. When a target memory block is bad, and the determining circuit of the memory controller generates the hit signal, the memory controller disables the redundant memory block that is bad according to the hit signal.
    Type: Grant
    Filed: November 2, 2021
    Date of Patent: June 20, 2023
    Assignee: Winbond Electronics Corp.
    Inventor: Jun-Lin Yeh
  • Publication number: 20220139493
    Abstract: A memory device including a memory cell array, a redundant fuse circuit and a memory controller is provided. The memory cell array includes multiple regular memory blocks and multiple redundant memory blocks. The redundant fuse circuit includes multiple fuse groups recording multiple repair information. Each repair information is associated with a corresponding one of the redundant memory blocks and includes a repair address, a first enable bit, and a second enable bit. The memory controller includes multiple determining circuits. Each of the multiple determining circuits generates a hit signal according to an operation address, the repair address, the first enable bit, and the second enable bit. When a target memory block is bad, and the determining circuit of the memory controller generates the hit signal, the memory controller disables the redundant memory block that is bad according to the hit signal.
    Type: Application
    Filed: November 2, 2021
    Publication date: May 5, 2022
    Applicant: Winbond Electronics Corp.
    Inventor: Jun-Lin Yeh
  • Patent number: 10762970
    Abstract: An inspection method for memory integrity, a non-volatile memory, and an electronic device are provided. The method includes following steps. A threshold voltage of at least one memory cell to-be-inspected in a non-volatile memory is obtained. A data value belonging to the at least one memory cell to-be-inspected is determined by comparing a read voltage and the threshold voltage. When the data value belonging to the at least one memory cell to-be-inspected is determined, a preset voltage is set according to the data value. An offset data value belonging to the at least one memory cell to-be-inspected is obtained by comparing the preset voltage and the threshold voltage of the at least one memory cell to-be-inspected. And, whether the data value and the offset data value belonging to the at least one memory cell to-be-inspected are the same is determined, so as to determine whether an integrity of the memory cell to-be-inspected is defective.
    Type: Grant
    Filed: May 17, 2018
    Date of Patent: September 1, 2020
    Assignee: Winbond Electronics Corp.
    Inventor: Jun-Lin Yeh
  • Patent number: 10566060
    Abstract: A memory device is provided and includes a status register, a memory array, a memory controller, an interface control circuit, and a write control logic circuit. The status register stores a plurality of status bits and a first threshold. The interface control circuit is controlled by the memory controller to perform a data program/erase operation on the memory array and re-program/re-erase the memory array in a retry mode when the data program/erase operation is not complete. The write control logic circuit counts the number of times the memory array is re-programmed/re-erased in the retry mode to generate a retry counting value, compares the retry counting value with the first threshold to generate a result signal. The status register updates a result bit included in the status bits according to the result signal. The memory controller determines whether the data program/erase operation is successful according to the result bit.
    Type: Grant
    Filed: December 24, 2018
    Date of Patent: February 18, 2020
    Assignee: Winbond Electronics Corp.
    Inventor: Jun-Lin Yeh
  • Publication number: 20190244670
    Abstract: A memory device is provided and includes a status register, a memory array, a memory controller, an interface control circuit, and a write control logic circuit. The status register stores a plurality of status bits and a first threshold. The interface control circuit is controlled by the memory controller to perform a data program/erase operation on the memory array and re-program/re-erase the memory array in a retry mode when the data program/erase operation is not complete. The write control logic circuit counts the number of times the memory array is re-programmed/re-erased in the retry mode to generate a retry counting value, compares the retry counting value with the first threshold to generate a result signal. The status register updates a result bit included in the status bits according to the result signal. The memory controller determines whether the data program/erase operation is successful according to the result bit.
    Type: Application
    Filed: December 24, 2018
    Publication date: August 8, 2019
    Inventor: Jun-Lin YEH
  • Publication number: 20190198122
    Abstract: An inspection method for memory integrity, a non-volatile memory, and an electronic device are provided. The method includes following steps. A threshold voltage of at least one memory cell to-be-inspected in a non-volatile memory is obtained. A data value belonging to the at least one memory cell to-be-inspected is determined by comparing a read voltage and the threshold voltage. When the data value belonging to the at least one memory cell to-be-inspected is determined, a preset voltage is set according to the data value. An offset data value belonging to the at least one memory cell to-be-inspected is obtained by comparing the preset voltage and the threshold voltage of the at least one memory cell to-be-inspected. And, whether the data value and the offset data value belonging to the at least one memory cell to-be-inspected are the same is determined, so as to determine whether an integrity of the memory cell to-be-inspected is defective.
    Type: Application
    Filed: May 17, 2018
    Publication date: June 27, 2019
    Applicant: Winbond Electronics Corp.
    Inventor: Jun-Lin Yeh
  • Patent number: 10249376
    Abstract: A flash memory storage device including a memory cell array and a memory control circuit is provided. The memory cell array includes a plurality of memory blocks and a redundant memory block. The memory blocks are configured to store data. The memory control circuit is coupled to the memory cell array. The memory control circuit is configured to perform an erase operation to a current memory block of the memory blocks and record an erase retry count of the current memory block. The memory control circuit determines whether the erase retry count exceeds a threshold value. If the erase retry count exceeds the threshold value, the memory control circuit replaces the current memory block by the redundant memory block erased in advance during a time interval of the erase operation. In addition, an operating method of a flash memory storage device is also provided.
    Type: Grant
    Filed: January 15, 2018
    Date of Patent: April 2, 2019
    Assignee: Winbond Electronics Corp.
    Inventor: Jun-Lin Yeh
  • Publication number: 20180336954
    Abstract: A flash memory storage device including a memory cell array and a memory control circuit is provided. The memory cell array includes a plurality of memory blocks and a redundant memory block. The memory blocks are configured to store data. The memory control circuit is coupled to the memory cell array. The memory control circuit is configured to perform an erase operation to a current memory block of the memory blocks and record an erase retry count of the current memory block. The memory control circuit determines whether the erase retry count exceeds a threshold value. If the erase retry count exceeds the threshold value, the memory control circuit replaces the current memory block by the redundant memory block erased in advance during a time interval of the erase operation. In addition, an operating method of a flash memory storage device is also provided.
    Type: Application
    Filed: January 15, 2018
    Publication date: November 22, 2018
    Applicant: Winbond Electronics Corp.
    Inventor: Jun-Lin Yeh
  • Patent number: 10113233
    Abstract: An apparatus and a method for controlling critical dimension (CD) of a circuit is provided. An apparatus includes a controller for receiving CD measurements at respective locations in a circuit pattern in an etched film on a first substrate and a single wafer chamber for forming a second film of the film material on a second substrate. The single wafer chamber is responsive to a signal from the controller to locally adjust a thickness of the second film based on the measured CD's. A method provides for etching a circuit pattern of a film on a first substrate, measuring CD's of the circuit pattern, adjusting a single wafer chamber to form a second film on a second semiconductor substrate based on the measured CD. The second film thickness is locally adjusted based on the measured CD's.
    Type: Grant
    Filed: April 7, 2015
    Date of Patent: October 30, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chun-Lin Chang, Hsin-Hsien Wu, Zin-Chang Wei, Chi-Ming Yang, Chyi Shyuan Chern, Jun-Lin Yeh, Jih-Jse Lin, Jo Fei Wang, Ming-Yu Fan, Jong-I Mou
  • Patent number: 9754831
    Abstract: Apparatus, and methods of manufacture thereof, in which metal is deposited into openings, thus forming a plurality of metal pads, a plurality of through-silicon-vias (TSVs), a plurality of metal lines, a plurality of first dummy structures, and a plurality of second dummy structures. Ones of the plurality of first dummy structures each have a first width that is at least about three times greater than a second width of each of the plurality of metal lines, and ones of the plurality of second dummy structures each have a third width that is at least about five times greater than the second width of each of the plurality of metal lines.
    Type: Grant
    Filed: August 22, 2016
    Date of Patent: September 5, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Pei-Ching Kuo, Yi-Hsiu Chen, Jun-Lin Yeh, Yung-Chi Lin, Li-Han Hsu, Wei-Cheng Wu, Ku-Feng Yang, Wen-Chih Chiou
  • Publication number: 20170022611
    Abstract: An apparatus and a method for controlling critical dimension (CD) of a circuit is provided. An apparatus includes a controller for receiving CD measurements at respective locations in a circuit pattern in an etched film on a first substrate and a single wafer chamber for forming a second film of the film material on a second substrate. The single wafer chamber is responsive to a signal from the controller to locally adjust a thickness of the second film based on the measured CD's. A method provides for etching a circuit pattern of a film on a first substrate, measuring CD's of the circuit pattern, adjusting a single wafer chamber to form a second film on a second semiconductor substrate based on the measured CD. The second film thickness is locally adjusted based on the measured CD's.
    Type: Application
    Filed: April 7, 2015
    Publication date: January 26, 2017
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chun-Lin CHANG, Hsin-Hsien WU, Zin-Chang WEI, Chi-Ming YANG, Chyi Shyuan CHERN, Jun-Lin YEH, Jih-Jse LIN, Jo Fei WANG, Ming-Yu FAN, Jong-I MOU
  • Publication number: 20160358818
    Abstract: Apparatus, and methods of manufacture thereof, in which metal is deposited into openings, thus forming a plurality of metal pads, a plurality of through-silicon-vias (TSVs), a plurality of metal lines, a plurality of first dummy structures, and a plurality of second dummy structures. Ones of the plurality of first dummy structures each have a first width that is at least about three times greater than a second width of each of the plurality of metal lines, and ones of the plurality of second dummy structures each have a third width that is at least about five times greater than the second width of each of the plurality of metal lines.
    Type: Application
    Filed: August 22, 2016
    Publication date: December 8, 2016
    Inventors: Pei-Ching Kuo, Yi-Hsiu Chen, Jun-Lin Yeh, Yung-Chi Lin, Li-Han Hsu, Wei-Cheng Wu, Ku-Feng Yang, Wen-Chih Chiou
  • Patent number: 9425126
    Abstract: Apparatus, and methods of manufacture thereof, in which metal is deposited into openings, thus forming a plurality of metal pads, a plurality of through-silicon-vias (TSVs), a plurality of metal lines, a plurality of first dummy structures, and a plurality of second dummy structures. Ones of the plurality of first dummy structures each have a first width that is at least about three times greater than a second width of each of the plurality of metal lines, and ones of the plurality of second dummy structures each have a third width that is at least about five times greater than the second width of each of the plurality of metal lines.
    Type: Grant
    Filed: May 29, 2014
    Date of Patent: August 23, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Pei-Ching Kuo, Yi-Hsiu Chen, Jun-Lin Yeh, Yung-Chi Lin, Li-Han Hsu, Wei-Cheng Wu, Ku-Feng Yang, Wen-Chih Chiou
  • Patent number: 9281020
    Abstract: A storage medium communicating with a memory controller sent a read command is disclosed. The storage medium includes a plurality of memory units. Each memory unit includes at least sixteen memory cells coupled to a word line and a plurality of bit lines. A controlling unit receives first address information according to the read command and generates a row read signal and a column read signal according to the first address information. A row decoding unit activates the word line according to the row read signal. A column decoding unit activates the bit lines according to the column read signal to output a plurality of storing bits stored in the sixteen memory cells. A read-out unit processes the storing bits to generate a plurality of reading bits. The controlling unit outputs the reading bits to the memory controller in serial.
    Type: Grant
    Filed: October 29, 2012
    Date of Patent: March 8, 2016
    Assignee: Winbond Electronics Corp.
    Inventor: Jun-Lin Yeh
  • Patent number: 9214495
    Abstract: A memory cell structure is provided. A first doping region is formed in a substrate. A second doping region is formed in the substrate. A first gate is formed on the substrate. The first and second doping regions and the first gate constitute a first transistor. A first word line is electrically connected to the first gate. The first word line firstly extends along a first direction and then along a second direction which is different from the first direction. A resistive layer is electrically connected to the first doping region. A conductive layer comprises a first source line and a bit line. The first source line is electrically connected to the second doping region, and the bit line is electrically connected to the resistive layer. The first and second doping regions extend along a third direction which is different from the first and second directions.
    Type: Grant
    Filed: September 5, 2014
    Date of Patent: December 15, 2015
    Assignee: Winbond Electronics Corp.
    Inventors: Jun-Lin Yeh, Im-Cheol Ha
  • Publication number: 20150348872
    Abstract: Apparatus, and methods of manufacture thereof, in which metal is deposited into openings, thus forming a plurality of metal pads, a plurality of through-silicon-vias (TSVs), a plurality of metal lines, a plurality of first dummy structures, and a plurality of second dummy structures. Ones of the plurality of first dummy structures each have a first width that is at least about three times greater than a second width of each of the plurality of metal lines, and ones of the plurality of second dummy structures each have a third width that is at least about five times greater than the second width of each of the plurality of metal lines.
    Type: Application
    Filed: May 29, 2014
    Publication date: December 3, 2015
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Pei-Ching Kuo, Yi-Hsiu Chen, Jun-Lin Yeh, Yung-Chi Lin, Li-Han Hsu, Wei-Cheng Wu, Ku-Feng Yang, Wen-Chih Chiou
  • Patent number: 9136008
    Abstract: A flash memory apparatus and a data reading method thereof are provided. A boost voltage greater than a pre-charge voltage is provided to a gate of a source discharge transistor when a data reading operation is performed on a memory unit, so as to enhance discharge capability of the source discharge transistor.
    Type: Grant
    Filed: July 1, 2014
    Date of Patent: September 15, 2015
    Assignee: Winbond Electronics Corp.
    Inventors: Jun-Lin Yeh, Shang-Wen Chang
  • Patent number: 9104401
    Abstract: A flash memory apparatus with serial interface is disclosed. The flash memory apparatus includes a command receiver, a command decoder and a core circuit. The command receiver sequentially receives a plurality of command data through the data input pin and the clock pin. The command decoder receives a command sequence formed by the command data, and compares the command sequence with a reference sequence to generate a reset signal. The core circuit receives the reset signal to activate a reset operation according to the reset signal.
    Type: Grant
    Filed: October 31, 2014
    Date of Patent: August 11, 2015
    Assignee: Winbond Electronics Corp.
    Inventors: Jun-Lin Yeh, Chi-Cheng Lin
  • Publication number: 20150211122
    Abstract: An apparatus and a method for controlling critical dimension (CD) of a circuit is provided. An apparatus includes a controller for receiving CD measurements at respective locations in a circuit pattern in an etched film on a first substrate and a single wafer chamber for forming a second film of the film material on a second substrate. The single wafer chamber is responsive to a signal from the controller to locally adjust a thickness of the second film based on the measured CD's. A method provides for etching a circuit pattern of a film on a first substrate, measuring CD's of the circuit pattern, adjusting a single wafer chamber to form a second film on a second semiconductor substrate based on the measured CD. The second film thickness is locally adjusted based on the measured CD's.
    Type: Application
    Filed: April 7, 2015
    Publication date: July 30, 2015
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chun-Lin CHANG, Hsin-Hsien WU, Zin-Chang WEI, Chi-Ming YANG, Chyi Shyuan CHERN, Jun-Lin YEH, Jih-Jse LIN, Jo Fei WANG, Ming-Yu FAN, Jong-I MOU
  • Patent number: 9023664
    Abstract: An apparatus and a method for controlling critical dimension (CD) of a circuit is provided. An apparatus includes a controller for receiving CD measurements at respective locations in a circuit pattern in an etched film on a first substrate and a single wafer chamber for forming a second film of the film material on a second substrate. The single wafer chamber is responsive to a signal from the controller to locally adjust a thickness of the second film based on the measured CD's. A method provides for etching a circuit pattern of a film on a first substrate, measuring CD's of the circuit pattern, adjusting a single wafer chamber to form a second film on a second semiconductor substrate based on the measured CD. The second film thickness is locally adjusted based on the measured CD's.
    Type: Grant
    Filed: February 26, 2013
    Date of Patent: May 5, 2015
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chun-Lin Chang, Hsin-Hsien Wu, Zin-Chang Wei, Chi-Ming Yang, Chyi-Shyuan Chern, Jun-Lin Yeh, Jih-Jse Lin, Jo-Fei Wang, Ming-Yu Fan, Jong-I Mou