Abstract: A memory system is divided into memory subsystems. Each subsystem includes a slave controller. Each slave controller is coupled to a serial link. A master controller is coupled to the slave controllers via the serial links, and the master controller is capable of initiating a memory access to a memory subsystem by communicating with the slave controller via the serial link. Each memory subsystem includes memory arrays coupled to the slave controller. Each memory array includes memory channels. Memory accesses to a memory array on a memory subsystem are interleaved by the slave controller between the memory channels, and memory accesses to a memory subsystem are striped by the slave controller between the memory arrays on the memory subsystem. Memory accesses are striped between memory subsystems by the master controller. The master controller and slave controllers communicate by sending link packets and protocol packets over the serial links.

Abstract: In a storage system including a write-back cache, dirty data can be flushed from the cache while a controller continues to service host I/O requests. A controller is capable of flushing all the dirty data in the cache to a storage device in response to an indication to do so, such as an indication of impending failure. The controller is further capable of responding to I/O requests from the host during the flushing of the dirty data. In particular, the controller is capable of responding to write requests from the host system by storing data on the storage device during the flushing of the dirty data.