Patents by Inventor Jun Okuno
Jun Okuno has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11972229Abstract: Semiconductor devices and multiply-accumulate operation devices are disclosed. In one example, a semiconductor device includes synapses in which a nonvolatile variable resistance element taking a first resistance value and a second resistance value lower than the first resistance value and a fixed resistance element having a resistance value higher than the second resistance value are connected in series. An output line outputs a sum of currents flowing through the plurality of synapses.Type: GrantFiled: March 15, 2019Date of Patent: April 30, 2024Assignees: Sony Group Corporation, Sony Semiconductor Solutions CorporationInventors: Toshiyuki Kobayashi, Rui Morimoto, Jun Okuno, Masanori Tsukamoto, Yusuke Shuto
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Publication number: 20230409843Abstract: The present disclosure relates to a semiconductor device capable of reducing energy consumption. Provided is a semiconductor device including: an input unit that inputs a charge; a computing unit that accumulates a charge from the input unit and performs an arithmetic operation; and an output unit that detects and outputs the charge accumulated in the computing unit, in which the computing unit includes an accumulation unit to which a plurality of pair units, each of which is a pair of the input unit and a gate unit, is connected, each of the plurality of pair units makes a charge input from the input unit to the accumulation unit variable, and the accumulation unit accumulates a charge input from each of the connected plurality of pair units. The present disclosure is, for example, applicable to an analog computing device.Type: ApplicationFiled: October 29, 2021Publication date: December 21, 2023Inventors: Hiroshi Yoshida, Jun Okuno, Hiroki Koga, Yusuke Shuto, Takeo Tsukamoto
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Publication number: 20230402119Abstract: The present disclosure relates to a semiconductor device enabling to suppress waste of energy consumption. There is provided a semiconductor device including: an input unit configured to input a charge; a memory unit configured to collect and accumulate a charge from the input unit; and an output unit configured to detect and output a charge accumulated in the memory unit. The memory unit includes a transfer unit to which a plurality of pairs of a gate unit and an accumulation unit is connected, the gate unit selects the accumulation unit that accumulates a charge, the transfer unit transfers a charge from the input unit to the accumulation unit selected by the gate unit, the accumulation unit accumulates a charge transferred from the transfer unit, and the transfer unit transfers a charge accumulated in the accumulation unit selected by the gate unit, to the output unit. The present disclosure can be applied to, for example, an analog memory device.Type: ApplicationFiled: October 27, 2021Publication date: December 14, 2023Inventors: HIROSHI YOSHIDA, JUN OKUNO, HIROKI KOGA, YUSUKE SHUTO, TAKEO TSUKAMOTO
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Patent number: 11837270Abstract: A ferroelectric memory is intended to reduce an applied voltage required at the times of writing and reading. A ferroelectric capacitor includes a ferroelectric film and a top electrode and a bottom electrode including materials with different work functions formed above and below the ferroelectric film. The transistor is connected to either the top electrode or the bottom electrode to select the ferroelectric capacitor. A drive control unit applies, at the times of writing and reading, a voltage lower than that at the time of erasing by a predetermined potential difference to the ferroelectric film.Type: GrantFiled: February 6, 2020Date of Patent: December 5, 2023Assignees: Sony Semiconductor Solutions Corporation, Sony Group CorporationInventors: Jun Okuno, Toshiyuki Kobayashi
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Publication number: 20230225133Abstract: A semiconductor storage device includes a field-effect transistor, an interlayer insulation film, a source contact, an opening, and a capacitor. The field-effect transistor is provided on a semiconductor substrate. The interlayer insulation film is provided on the semiconductor substrate. The source contact runs through the interlayer insulation film and is electrically coupled to a source of the field-effect transistor. The opening is provided in a region of the interlayer insulation film including the source contact and allows the source contact to project therein. The capacitor includes a lower electrode, a ferroelectric film, and an upper electrode. The lower electrode is provided along an inside shape of the opening. The ferroelectric film is provided on the lower electrode. The upper electrode is provided on the ferroelectric film to fill the opening.Type: ApplicationFiled: April 30, 2021Publication date: July 13, 2023Inventor: JUN OKUNO
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Publication number: 20230225134Abstract: There is provided a semiconductor storage device that is allowed to obtain a sufficient margin for operation. The semiconductor storage device includes: a field-effect transistor; an interlayer insulating film; a contact; a first wiring layer; a first insulating layer; an opening section; and a ferroelectric capacitor. The field-effect transistor is provided in a semiconductor substrate. The interlayer insulating film is provided on the semiconductor substrate. The contact penetrates the interlayer insulating film and is electrically coupled to a drain of the field-effect transistor. The first wiring layer is provided on the contact. The first insulating layer is provided on the interlayer insulating film and has the first wiring layer buried therein. The opening section is provided in the first insulating layer and the interlayer insulating film from a layer upper than the first wiring layer.Type: ApplicationFiled: June 3, 2021Publication date: July 13, 2023Inventors: MASANORI TSUKAMOTO, JUN OKUNO
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Patent number: 11621285Abstract: The present technology relates to a solid-state imaging device and a driving method thereof, and an electronic apparatus that make it possible to improve the precision of phase difference detection while suppressing deterioration of resolution in a solid-state imaging device having a global shutter function and a phase difference AF function. Provided is a solid-state imaging device including: a pixel array unit including, as pixels including an on-chip lens, a photoelectric conversion unit, and a charge accumulation unit, imaging pixels for generating a captured image and phase difference detection pixels for performing phase difference detection arrayed therein; and a driving control unit configured to control driving of the pixels. The imaging pixel is formed with the charge accumulation unit shielded from light.Type: GrantFiled: March 30, 2021Date of Patent: April 4, 2023Assignee: SONY CORPORATIONInventors: Jun Okuno, Kazuyoshi Yamashita
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Publication number: 20220189525Abstract: A ferroelectric memory is intended to reduce an applied voltage required at the times of writing and reading. A ferroelectric capacitor includes a ferroelectric film and a top electrode and a bottom electrode including materials with different work functions formed above and below the ferroelectric film. The transistor is connected to either the top electrode or the bottom electrode to select the ferroelectric capacitor. A drive control unit applies, at the times of writing and reading, a voltage lower than that at the time of erasing by a predetermined potential difference to the ferroelectric film.Type: ApplicationFiled: February 6, 2020Publication date: June 16, 2022Applicants: SONY SEMICONDUCTOR SOLUTIONS CORPORATION, SONY GROUP CORPORATIONInventors: Jun OKUNO, Toshiyuki KOBAYASHI
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Patent number: 11211123Abstract: A disclosed semiconductor device includes a memory cell with a first terminal, a second terminal, a memory element having a first resistance state and a second resistance state, and a nonlinear element, and a drive controller that performs a first operation that allows the memory element to be in the first resistance state, a second operation that allows the memory element to be in the second resistance state, a third operation in which the voltage of the first and second terminals is caused to be different from each other and a value of electric current flowing between the first terminal and the second terminal is caused to be limited to a first current value to determine the resistance state, and a fourth operation in which the current value is caused to be limited to a second current value. The drive controller performs the fourth operation after at least one of the first to third operations.Type: GrantFiled: November 30, 2018Date of Patent: December 28, 2021Assignee: Sony Semiconductor Solutions CorporationInventors: Takeyuki Sone, Seiji Nonoguchi, Jun Okuno, Hiroyuki Fujita
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Publication number: 20210217791Abstract: The present technology relates to a solid-state imaging device and a driving method thereof, and an electronic apparatus that make it possible to improve the precision of phase difference detection while suppressing deterioration of resolution in a solid-state imaging device having a global shutter function and a phase difference AF function. Provided is a solid-state imaging device including: a pixel array unit including, as pixels including an on-chip lens, a photoelectric conversion unit, and a charge accumulation unit, imaging pixels for generating a captured image and phase difference detection pixels for performing phase difference detection arrayed therein; and a driving control unit configured to control driving of the pixels. The imaging pixel is formed with the charge accumulation unit shielded from light.Type: ApplicationFiled: March 30, 2021Publication date: July 15, 2021Applicant: Sony CorporationInventors: Jun Okuno, Kazuyoshi Yamashita
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Publication number: 20210183443Abstract: A disclosed semiconductor device includes a memory cell with a first terminal, a second terminal, a memory element having a first resistance state and a second resistance state, and a nonlinear element, and a drive controller that performs a first operation that allows the memory element to be in the first resistance state, a second operation that allows the memory element to be in the second resistance state, a third operation in which the of of the first and second terminals is caused to be different from each other and a value of electric current flowing between the first terminal and the second terminal is caused to be limited to a first current value to determine the resistance state, and a fourth operation in which the current value is caused to be limited to a second current value. The drive controller performs the fourth operation after at least one of the first to third operations.Type: ApplicationFiled: November 30, 2018Publication date: June 17, 2021Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATIONInventors: Takeyuki SONE, Seiji NONOGUCHI, Jun OKUNO, Hiroyuki FUJITA
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Patent number: 11024376Abstract: A memory apparatus includes a memory cell disposed at an intersection of a first wiring line and a second wiring line, and including a variable resistor and a selector, the variable resistor having a resistance state that changes to a first resistance state and a second resistance state, and a drive circuit that writes data to the memory cell by changing the variable resistor from the first resistance state to the second resistance state, and erases the data stored in the memory cell by changing the variable resistor from the second resistance state to the first resistance state. When erasing the data, the drive circuit changing in a stepwise manner a voltage applied to the memory cell, and changing in a stepwise manner a current limit value that limits a magnitude of a current flowing through the memory cell.Type: GrantFiled: May 11, 2018Date of Patent: June 1, 2021Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATIONInventors: Yotaro Mori, Makoto Kitagawa, Jun Okuno, Haruhiko Terada
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Patent number: 11004902Abstract: Provided is a circuit element that includes paired inert electrodes, and a switch layer provided between the paired inert electrodes, that functions as a selection element and a storage element as a single layer, and having a differential negative resistance region in a current-voltage characteristic.Type: GrantFiled: April 24, 2017Date of Patent: May 11, 2021Assignee: SONY CORPORATIONInventors: Minoru Ikarashi, Seiji Nonoguchi, Takeyuki Sone, Hiroaki Sei, Kazuhiro Ohba, Jun Okuno
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Patent number: 10998356Abstract: The present technology relates to a solid-state imaging device and a driving method thereof, and an electronic apparatus that make it possible to improve the precision of phase difference detection while suppressing deterioration of resolution in a solid-state imaging device having a global shutter function and a phase difference AF function. Provided is a solid-state imaging device including: a pixel array unit including, as pixels including an on-chip lens, a photoelectric conversion unit, and a charge accumulation unit, imaging pixels for generating a captured image and phase difference detection pixels for performing phase difference detection arrayed therein; and a driving control unit configured to control driving of the pixels. The imaging pixel is formed with the charge accumulation unit shielded from light.Type: GrantFiled: December 18, 2019Date of Patent: May 4, 2021Assignee: SONY CORPORATIONInventors: Jun Okuno, Kazuyoshi Yamashita
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Publication number: 20210026601Abstract: [Problem] Provided are a semiconductor device and a multiply-accumulate operation device that enable integration at a higher density by further reducing a mounting area per synapse. [Solution] A semiconductor device including: a plurality of synapses in which a nonvolatile variable resistance element taking a first resistance value and a second resistance value lower than the first resistance value and a fixed resistance element having a resistance value higher than the second resistance value are connected in series; and an output line that outputs a sum of currents flowing through the plurality of synapses. [Selected Drawing] FIG.Type: ApplicationFiled: March 15, 2019Publication date: January 28, 2021Inventors: Toshiyuki Kobayashi, Rui Morimoto, Jun Okuno, Masanori Tsukamoto, Yusuke Shuto
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Publication number: 20210013219Abstract: A semiconductor storage device and a multiplier-accumulator are provided that are capable of applying a sufficient voltage to a ferroelectric capacitor and are suitable for high integration. A semiconductor storage device includes: a transistor; and a ferroelectric capacitor that is formed by sandwiching a ferroelectric material between a pair of conductive materials, one of the pair of conductive materials being electrically connected to a gate electrode of the transistor, in which a channel of the transistor is three-dimensionally formed over a plurality of surfaces.Type: ApplicationFiled: March 12, 2019Publication date: January 14, 2021Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATIONInventors: Jun OKUNO, Fumitaka SUGAYA, Masanori TSUKAMOTO
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Publication number: 20200127028Abstract: The present technology relates to a solid-state imaging device and a driving method thereof, and an electronic apparatus that make it possible to improve the precision of phase difference detection while suppressing deterioration of resolution in a solid-state imaging device having a global shutter function and a phase difference AF function. Provided is a solid-state imaging device including: a pixel array unit including, as pixels including an on-chip lens, a photoelectric conversion unit, and a charge accumulation unit, imaging pixels for generating a captured image and phase difference detection pixels for performing phase difference detection arrayed therein; and a driving control unit configured to control driving of the pixels. The imaging pixel is formed with the charge accumulation unit shielded from light.Type: ApplicationFiled: December 18, 2019Publication date: April 23, 2020Applicant: Sony CorporationInventors: Jun Okuno, Kazuyoshi Yamashita
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Publication number: 20200098425Abstract: A memory apparatus includes a memory cell disposed at an intersection of a first wiring line and a second wiring line, and including a variable resistor and a selector, the variable resistor having a resistance state that changes to a first resistance state and a second resistance state, and a drive circuit that writes data to the memory cell by changing the variable resistor from the first resistance state to the second resistance state, and erases the data stored in the memory cell by changing the variable resistor from the second resistance state to the first resistance state. When erasing the data, the drive circuit changing in a stepwise manner a voltage applied to the memory cell, and changing in a stepwise manner a current limit value that limits a magnitude of a current flowing through the memory cell.Type: ApplicationFiled: May 11, 2018Publication date: March 26, 2020Inventors: YOTARO MORI, MAKOTO KITAGAWA, JUN OKUNO, HARUHIKO TERADA
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Patent number: 10559609Abstract: The present technology relates to a solid-state imaging device and a driving method thereof, and an electronic apparatus that make it possible to improve the precision of phase difference detection while suppressing deterioration of resolution in a solid-state imaging device having a global shutter function and a phase difference AF function. Provided is a solid-state imaging device including: a pixel array unit including, as pixels including an on-chip lens, a photoelectric conversion unit, and a charge accumulation unit, imaging pixels for generating a captured image and phase difference detection pixels for performing phase difference detection arrayed therein; and a driving control unit configured to control driving of the pixels. The imaging pixel is formed with the charge accumulation unit shielded from light.Type: GrantFiled: January 10, 2019Date of Patent: February 11, 2020Assignee: Sony CorporationInventors: Jun Okuno, Kazuyoshi Yamashita
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Patent number: 10559608Abstract: The present technology relates to a solid-state imaging device and a driving method thereof, and an electronic apparatus that make it possible to improve the precision of phase difference detection while suppressing deterioration of resolution in a solid-state imaging device having a global shutter function and a phase difference AF function. Provided is a solid-state imaging device including: a pixel array unit including, as pixels including an on-chip lens, a photoelectric conversion unit, and a charge accumulation unit, imaging pixels for generating a captured image and phase difference detection pixels for performing phase difference detection arrayed therein; and a driving control unit configured to control driving of the pixels. The imaging pixel is formed with the charge accumulation unit shielded from light.Type: GrantFiled: January 9, 2019Date of Patent: February 11, 2020Assignee: Sony CorporationInventors: Jun Okuno, Kazuyoshi Yamashita