Patents by Inventor Jun-Phyo Lee
Jun-Phyo Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240161851Abstract: A test system includes a test device configured to output a command address and a test dock for performing a test mode and to receive a comparison signal, and a memory device configured to enter the test mode, based on the command address, to set an initial value by the command address, to perform a calculation operation on the initial value according to a logic level combination of the command address to generate a row address and a command address during a pre-charge operation, and to compress and compare internal data output based on the row address and the column address to output the internal data as the comparison signal to the test device.Type: ApplicationFiled: March 1, 2023Publication date: May 16, 2024Applicant: SK hynix Inc.Inventors: Sang Ah HYUN, Yong Ho SEO, Woo Sik JUNG, Jun Phyo LEE, Bong Hwa JEONG
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Patent number: 11367467Abstract: A semiconductor device may include a plurality of memory banks arranged in a first direction; an address decoder arranged at one side of the memory banks; a plurality of local sense amplifier arrays arranged under each of the memory banks; a plurality of first input/output lines connected between the memory banks and the local sense amplifier arrays corresponding to each of the memory banks; and at least one second input/output line connected to the local sense amplifier arrays and extended in the first direction.Type: GrantFiled: July 24, 2020Date of Patent: June 21, 2022Assignee: SK hynix Inc.Inventors: Hyung Sik Won, Seung Han Oak, Jun Phyo Lee
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Publication number: 20200365191Abstract: A semiconductor device may include a plurality of memory banks arranged in a first direction; an address decoder arranged at one side of the memory banks; a plurality of local sense amplifier arrays arranged under each of the memory banks; a plurality of first input/output lines connected between the memory banks and the local sense amplifier arrays corresponding to each of the memory banks; and at least one second input/output line connected to the local sense amplifier arrays and extended in the first direction.Type: ApplicationFiled: July 24, 2020Publication date: November 19, 2020Inventors: Hyung Sik WON, Seung Han OAK, Jun Phyo LEE
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Patent number: 10762930Abstract: A semiconductor device may include a plurality of memory banks arranged in a first direction; an address decoder arranged at one side of the memory banks; a plurality of local sense amplifier arrays arranged under each of the memory banks; a plurality of first input/output lines connected between the memory banks and the local sense amplifier arrays corresponding to each of the memory banks; and at least one second input/output line connected to the local sense amplifier arrays and extended in the first direction.Type: GrantFiled: August 14, 2018Date of Patent: September 1, 2020Assignee: SK hynix Inc.Inventors: Hyung Sik Won, Seung Han Oak, Jun Phyo Lee
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Publication number: 20190214057Abstract: A semiconductor device may include a plurality of memory banks arranged in a first direction; an address decoder arranged at one side of the memory banks; a plurality of local sense amplifier arrays arranged under each of the memory banks; a plurality of first input/output lines connected between the memory banks and the local sense amplifier arrays corresponding to each of the memory banks; and at least one second input/output line connected to the local sense amplifier arrays and extended in the first direction.Type: ApplicationFiled: August 14, 2018Publication date: July 11, 2019Inventors: Hyung Sik WON, Seung Han OAK, Jun Phyo LEE
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Patent number: 9911706Abstract: A semiconductor device includes a main pad part and a sub pad part formed in a peripheral area of at least one side of the main pad part. The sub pad part is spaced apart from the main pad part. The sub pad part operates in a first state in which the sub pad part is short-circuited with the main pad part or in a second state in which the sub pad part is open from the main pad part.Type: GrantFiled: July 1, 2015Date of Patent: March 6, 2018Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Chang-hyun Cho, Jun-phyo Lee, Yong-hwan Jeong
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Publication number: 20160133586Abstract: A semiconductor device includes a main pad part and a sub pad part formed in a peripheral area of at least one side of the main pad part. The sub pad part is spaced apart from the main pad part. The sub pad part operates in a first state in which the sub pad part is short-circuited with the main pad part or in a second state in which the sub pad part is open from the main pad part.Type: ApplicationFiled: July 1, 2015Publication date: May 12, 2016Inventors: Chang-hyun CHO, Jun-phyo LEE, Yong-hwan JEONG
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Patent number: 8395953Abstract: The bit-line sense amplifier includes a driving-voltage control circuit and an amplifier. The driving-voltage control circuit generates a first test driving voltage having a voltage level of a pre-charge voltage, a second test driving voltage having a voltage level of a pre-charge voltage added by a voltage difference between a bit-line and a complementary bit-line, and a third test driving voltage having a voltage level of a pre-charge voltage subtracted by the voltage difference in a test mode. The amplifier senses and amplifies a voltage difference between the bit-line and the complementary bit-line.Type: GrantFiled: December 2, 2010Date of Patent: March 12, 2013Assignee: Samsung Electronics Co., Ltd.Inventors: Cheol Kim, Sang-Kyun Park, Jung-Bae Lee, Jun-Phyo Lee
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Patent number: 8379477Abstract: Provided is a semiconductor memory device including a sub-word-line driving circuit capable of reducing an amount of leakage current due to coupling. The semiconductor memory device includes a word-line enable signal generating circuit and a sub-word-line driving circuit. The sub-word-line driving circuit provides a pull-down current path between a selected word line and ground for a pulse type period of time in a precharge mode following an active mode for the selected word line, generates a word line driving signal on the basis of a main word line driving signal, a first sub-word-line control signal, and a second sub-word-line control signal, and provides the word line driving signal to a memory cell array. The semiconductor memory device may reduce an amount of leakage current flowing to a ground through the sub-word-line driving circuit.Type: GrantFiled: February 2, 2011Date of Patent: February 19, 2013Assignee: Samsung Electronics Co., Ltd.Inventors: Cheol Kim, Sang-Kyun Park, Jung-Bae Lee, Jun-Phyo Lee
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Patent number: 8125846Abstract: An internal voltage generating circuit of a semiconductor memory device includes a driving current generator that controls the magnitude of a driving current and supplies a controlled driving current in response to signals activated according to an operational mode. A comparison voltage generator receives a reference voltage and an internal power supply voltage, outputs a differentially amplified comparison voltage in response to a voltage difference between the reference voltage and the internal power supply voltage, and operates according to the driving current. A bulk bias controller receives at least two voltages and selectively outputs a voltage as a bulk bias voltage in response to a power-down enable signal, a normal enable signal, and an operating enable signal. An internal voltage driver controls a threshold voltage in response to the bulk bias voltage, controls a current amount in response to the comparison voltage, and outputs the internal power supply voltage.Type: GrantFiled: January 19, 2010Date of Patent: February 28, 2012Assignee: Samsung Electronics Co., Ltd.Inventor: Jun-Phyo Lee
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Publication number: 20110228624Abstract: Provided is a semiconductor memory device including a sub-word-line driving circuit capable of reducing an amount of leakage current due to coupling. The semiconductor memory device includes a word-line enable signal generating circuit and a sub-word-line driving circuit. The sub-word-line driving circuit provides a pull-down current path between a selected word line and ground for a pulse type period of time in a precharge mode following an active mode for the selected word line, generates a word line driving signal on the basis of a main word line driving signal, a first sub-word-line control signal, and a second sub-word-line control signal, and provides the word line driving signal to a memory cell array. The semiconductor memory device may reduce an amount of leakage current flowing to a ground through the sub-word-line driving circuit.Type: ApplicationFiled: February 2, 2011Publication date: September 22, 2011Inventors: Cheol Kim, Sang-Kyun Park, Jung-Bae Lee, Jun-Phyo Lee
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Publication number: 20110199836Abstract: The bit-line sense amplifier includes a driving-voltage control circuit and an amplifier. The driving-voltage control circuit generates a first test driving voltage having a voltage level of a pre-charge voltage, a second test driving voltage having a voltage level of a pre-charge voltage added by a voltage difference between a bit-line and a complementary bit-line, and a third test driving voltage having a voltage level of a pre-charge voltage subtracted by the voltage difference in a test mode. The amplifier senses and amplifies a voltage difference between the bit-line and the complementary bit-line.Type: ApplicationFiled: December 2, 2010Publication date: August 18, 2011Inventors: Cheol Kim, Sang-Kyun Park, Jung-Bae Lee, Jun-Phyo Lee
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Patent number: 7973526Abstract: A reference voltage generator for improving setup voltage characteristics without an increase in a standby current and a method of controlling the same, in which the reference voltage generator includes: a reference voltage generation unit including a resistor connected between a power supply voltage and an output node, for dividing the power voltage, and generating a reference voltage fed to the output node thereof; a voltage detector receiving a feedback of the reference voltage and detecting a level of the reference voltage; and a bypass circuit connected in parallel to the resistor of the reference voltage generation unit and bypassing the resistor in response to an output signal of the voltage detector.Type: GrantFiled: February 27, 2008Date of Patent: July 5, 2011Assignee: Samsung Electronics Co., Ltd.Inventor: Jun-phyo Lee
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Publication number: 20100182867Abstract: An internal voltage generating circuit of a semiconductor memory device includes a driving current generator that controls the magnitude of a driving current and supplies a controlled driving current in response to signals activated according to an operational mode. A comparison voltage generator receives a reference voltage and an internal power supply voltage, outputs a differentially amplified comparison voltage in response to a voltage difference between the reference voltage and the internal power supply voltage, and operates according to the driving current. A bulk bias controller receives at least two voltages and selectively outputs a voltage as a bulk bias voltage in response to a power-down enable signal, a normal enable signal, and an operating enable signal. An internal voltage driver controls a threshold voltage in response to the bulk bias voltage, controls a current amount in response to the comparison voltage, and outputs the internal power supply voltage.Type: ApplicationFiled: January 19, 2010Publication date: July 22, 2010Inventor: Jun-Phyo Lee
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Patent number: 7750729Abstract: An internal voltage generator is disclosed. The internal voltage generator may include a comparator for controlling a voltage of a first node in response to a voltage difference between a reference voltage and an internal voltage, an internal voltage driving portion connected between a driving node and an internal voltage node to apply the internal voltage to the internal voltage node in response to a voltage level of the first node, and/or a leakage current interrupting portion to apply an external voltage to the first node to deactivate the internal voltage driving portion and to interrupt the external voltage applied to the driving node to interrupt a leakage current.Type: GrantFiled: February 27, 2008Date of Patent: July 6, 2010Assignee: Samsung Electronics Co., Ltd.Inventors: Jun-Phyo Lee, Young-Gu Kang, Beob-Rae Cho
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Publication number: 20080204125Abstract: An internal voltage generator is disclosed. The internal voltage generator may include a comparator for controlling a voltage of a first node in response to a voltage difference between a reference voltage and an internal voltage, an internal voltage driving portion connected between a driving node and an internal voltage node to apply the internal voltage to the internal voltage node in response to a voltage level of the first node, and/or a leakage current interrupting portion to apply an external voltage to the first node to deactivate the internal voltage driving portion and to interrupt the external voltage applied to the driving node to interrupt a leakage current.Type: ApplicationFiled: February 27, 2008Publication date: August 28, 2008Inventors: Jun-Phyo Lee, Young-Gu Kang, Beob-Rae Cho
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Publication number: 20080203987Abstract: A reference voltage generator for improving setup voltage characteristics without an increase in a standby current and a method of controlling the same, in which the reference voltage generator includes: a reference voltage generation unit including a resistor connected between a power supply voltage and an output node, for dividing the power voltage, and generating a reference voltage fed to the output node thereof; a voltage detector receiving a feedback of the reference voltage and detecting a level of the reference voltage; and a bypass circuit connected in parallel to the resistor of the reference voltage generation unit and bypassing the resistor in response to an output signal of the voltage detector.Type: ApplicationFiled: February 27, 2008Publication date: August 28, 2008Inventor: Jun-phyo Lee