Abstract: A resist composition comprising a base polymer comprising repeat units having a salt structure consisting of a sulfonic acid anion bonded to a polymer backbone and a sulfonium cation having formula (1).

Abstract: A resist composition comprising a sulfonium salt composed of a sulfonate anion having a carbon atom to which an iodine atom is bonded and a sulfonium cation having the formula (1) exhibits a high sensitivity and reduced LWR or improved CDU.

Abstract: A semiconductor substrate including plural types of semiconductor layers exposed at a surface thereof is provided. A semiconductor substrate includes: a supporting substrate; a single-crystal, first semiconductor layer disposed on a surface of the supporting substrate; a single-crystal, second semiconductor layer disposed on parts of a surface of the first semiconductor layer; and a single-crystal, third semiconductor layer disposed on those parts of the surface of the first semiconductor layer on which the second semiconductor layer is not disposed. The third semiconductor layer has a crystal orientation aligned with that of the first semiconductor layer and is made of the same material as the first semiconductor layer.

Abstract: A design support method for causing a computer using layout data for providing a layout in which macro cells are arranged and in which power supply wirings are formed at certain intervals in each wiring layer to execute, the method including: extracting a set of adjacent macro cells from the layout data; specifying a region located between macro cells that constitute the set of adjacent macro cells extracted in the extracting step from among row regions included in the layout represented by the layout data; detecting a power supply wiring of a specific wiring layer in a projection area located above the region specified in the specifying step, the specific wiring layer being higher than a bottom layer of the layout represented by the layout data; and outputting a region where no power supply wiring of the specific wiring layer is detected in the detecting step.

Abstract: A design support method for causing a computer using layout data for providing a layout in which macro cells are arranged and in which power supply wirings are formed at certain intervals in each wiring layer to execute, the method including: extracting a set of adjacent macro cells from the layout data; specifying a region located between macro cells that constitute the set of adjacent macro cells extracted in the extracting step from among row regions included in the layout represented by the layout data; detecting a power supply wiring of a specific wiring layer in a projection area located above the region specified in the specifying step, the specific wiring layer being higher than a bottom layer of the layout represented by the layout data; and outputting a region where no power supply wiring of the specific wiring layer is detected in the detecting step.

Abstract: A design support method for causing a computer using layout data for providing a layout in which macro cells are arranged and in which power supply wirings are formed at certain intervals in each wiring layer to execute, the method including: extracting a set of adjacent macro cells from the layout data; specifying a region located between macro cells that constitute the set of adjacent macro cells extracted in the extracting step from among row regions included in the layout represented by the layout data; detecting a power supply wiring of a specific wiring layer in a projection area located above the region specified in the specifying step, the specific wiring layer being higher than a bottom layer of the layout represented by the layout data; and outputting a region where no power supply wiring of the specific wiring layer is detected in the detecting step.

Abstract: A design support method for causing a computer using layout data for providing a layout in which macro cells are arranged and in which power supply wirings are formed at certain intervals in each wiring layer to execute, the method including: extracting a set of adjacent macro cells from the layout data; specifying a region located between macro cells that constitute the set of adjacent macro cells extracted in the extracting step from among row regions included in the layout represented by the layout data; detecting a power supply wiring of a specific wiring layer in a projection area located above the region specified in the specifying step, the specific wiring layer being higher than a bottom layer of the layout represented by the layout data; and outputting a region where no power supply wiring of the specific wiring layer is detected in the detecting step.

Abstract: One atomic layer of Si atoms 3 is grown on an Si-terminated SiC surface 1a having an Si polar face, and one atomic layer of C atoms 5 is further grown thereon. Then, Si and C are supplied to form an SiC layer. The surface of the SiC layer thus grown is a C polar face opposite to the Si polar face. That is, according to the above-described step, it is possible to grow an SiC polarity-reversed layer 1x having a C polarity on an SiC layer 1 having an Si polarity, with one atomic layer of an Si intermediate layer b interposed therebetween. Consequently, it is possible to provide a technique to reverse the polarity of SiC on the surface.

Abstract: SiC is a very stable substance, and it is difficult to control the condition of a SiC surface to be suitable for crystal growth in conventional Group III nitride crystal growing apparatuses. This problem is solved as follows. The surface of a SiC substrate 1 is rendered into a step-terrace structure by performing a heating process in an atmosphere of HCl gas. The surface of the SiC substrate 1 is then treated sequentially with aqua regia, hydrochloric acid, and hydrofluoric acid. A small amount of silicon oxide film formed on the surface of the SiC substrate 1 is etched so as to form a clean SiC surface 3 on the substrate surface. The SiC substrate 1 is then installed in a high-vacuum apparatus and the pressure inside is maintained at ultrahigh vacuum (such as 10?6 to 10?8 Pa). In the ultrahigh vacuum state, a process of irradiating the surface with a Ga atomic beam 5 at time t1 at temperature of 800° C. or lower and performing a heating treatment at 800° C. or higher is repeated at least once.

Abstract: A field effect transistor comprises a SiC substrate 1, a source 3a and a drain 3b formed on the surface of the SiC substrate 1, an insulating structure comprising an AlN layer 5 formed in contact with the SiC surface and having a thickness of one molecule-layer or greater, and a SiO2 layer formed thereon, and a gate electrode 15 formed on the insulation structure. Leakage current can be controlled while the state of interface with SiC is maintained in a good condition.

Abstract: 4H—InGaAlN alloy based optoelectronic and electronic devices on non-polar face are formed on 4H—AlN or 4H—AlGaN on (11-20) a-face 4H—SiC substrates. Typically, non polar 4H—AlN is grown on 4H—SiC (11-20) by molecular beam epitaxy (MBE). Subsequently, III-V nitride device layers are grown by metal organic chemical vapor deposition (MOCVD) with 4H-polytype for all of the layers. The non-polar device does not contain any built-in electric field due to the spontaneous and piezoelectric polarization. The optoelectronic devices on the non-polar face exhibits higher emission efficiency with shorter emission wavelength because the electrons and holes are not spatially separated in the quantum well. Vertical device configuration for lasers and light emitting diodes (LEDs) using conductive 4H—AlGaN interlayer on conductive 4H—SiC substrates makes the chip size and series resistance smaller. The elimination of such electric field also improves the performance of high speed and high power transistors.

Abstract: In the present invention, a technology for causing arbitrary polarity, crystal face and crystal orientation to exist mixedly in a plane on the surface of a SiC substrate, and for forming a SiC layer or a group III-nitride or group II-oxide layer on the surface, is provided. A first SiC substrate 41 having (0001) face and a second SiC substrate 44 having (000-1) face are prepared. An oxide film 43 is formed on the surfaces of the SiC substrates 41 and 44 by subjecting them to an oxidation treatment, and then the two SiC substrates are fusion-bonded so that the rear surface of the second SiC substrate and the surface of the first SiC substrate are brought into contact with each other. Subsequently, a part corresponding to the second SiC substrate 44 is made thin (44a). Subsequently, a thin layer 44a of the second SiC substrate is removed in accordance with required periodic reversal to be processed in stripes by using a lithography technology and reactive ion etching technology.

Abstract: Disclosed are a diboride single crystal substrate which has a cleavage plane as same as that of a nitride compound semiconductor and is electrically conductive; a semiconductor laser diode and a semiconductor device using such a substrate and methods of their manufacture wherein the substrate is a single crystal substrate 1 of diboride XB2 (where X is either Zr or Ti) which is facially oriented in a (0001) plane 2 and has a thickness of 0.1 mm or less. The substrate 1 is permitted cleaving and splitting along a (10-10) plane 4 with ease. Using this substrate to form a semiconductor laser diode of a nitride compound, a vertical structure device can be realized. Resonant planes of a semiconductor laser diode with a minimum of loss can be fabricated by splitting the device in a direction parallel to the (10-10) plane. A method of manufacture that eliminates a margin of cutting is also realized.

Abstract: A field effect transistor comprises a SiC substrate 1, a source 3a and a drain 3b formed on the surface of the SiC substrate 1, an insulating structure comprising an AlN layer 5 formed in contact with the SiC surface and having a thickness of one molecule-layer or greater, and a SiO2 layer formed thereon, and a gate electrode 15 formed on the insulation structure. Leakage current can be controlled while the state of interface with SiC is maintained in a good condition.

Abstract: SiC is a very stable substance, and it is difficult to control the condition of a SiC surface to be suitable for crystal growth in conventional Group III nitride crystal growing apparatuses. This problem is solved as follows. The surface of a SiC substrate 1 is rendered into a step-terrace structure by performing a heating process in an atmosphere of HCl gas. The surface of the SiC substrate 1 is then treated sequentially with aqua regia, hydrochloric acid, and hydrofluoric acid. A small amount of silicon oxide film formed on the surface of the SiC substrate 1 is etched so as to form a clean SiC surface 3 on the substrate surface. The SiC substrate 1 is then installed in a high-vacuum apparatus and the pressure inside is maintained at ultrahigh vacuum (such as 10?6 to 10?8 Pa). In the ultrahigh vacuum state, a process of irradiating the surface with a Ga atomic beam 5 at time t1 at temperature of 800° C. or lower and performing a heating treatment at 800° C. or higher is repeated at least once.

Abstract: Disclosed are a diboride single crystal substrate which has a cleavage plane as same as that of a nitride compound semiconductor and is electrically conductive; a semiconductor laser diode and a semiconductor device using such a substrate and methods of their manufacture wherein the substrate is a single crystal substrate 1 of diboride XB2 (where X is either Zr or Ti) which is facially oriented in a (0001) plane 2 and has a thickness of 0.1 mm or less. The substrate 1 is permitted cleaving and splitting along a (10-10) plane 4 with ease. Using this substrate to form a semiconductor laser diode of a nitride compound, a vertical structure device can be realized. Resonant planes of a semiconductor laser diode with a minimum of loss can be fabricated by splitting the device in a direction parallel to the (10-10) plane. A method of manufacture that eliminates a margin of cutting is also realized.

Abstract: 4H-InGaAlN alloy based optoelectronic and electronic devices on non-polar face are formed on 4H-AlN or 4H-AlGaN on (11-20) a-face 4H-SiC substrates. Typically, non polar 4H-AlN is grown on 4H-SiC (11-20) by molecular beam epitaxy (MBE). Subsequently, III-V nitride device layers are grown by metal organic chemical vapor deposition (MOCVD) with 4H-polytype for all of the layers. The non-polar device does not contain any built-in electric field due to the spontaneous and piezoelectric polarization. The optoelectonic devices on the non-polar face exhibits higher emission efficiency with shorter emission wavelength because the electrons and holes are not spatially separated in the quantum well. Vertical device configuration for lasers and light emitting diodes(LEDs) using conductive 4H-AlGaN interlayer on conductive 4H-SiC substrates makes the chip size and series resistance smaller. The elimination of such electric field also improves the performance of high speed and high power transistors.

Abstract: Disclosed are a group III-nitride semiconductor substrate and a production method therefor. A group III-nitride semiconductor substrate having an element-forming surface with a dislocation density of 107 cm?2 or less in its entirely is formed only two steps. In a first step, a AlGaN-based low-temperature buffer layer is formed on a ZrB2 single crystal base having a defect density of 107 cm?2 or less, at a base temperature allowing the low-temperature buffer layer to be grown or deposited on the ZrB2 single crystal base substantially without creation of any Zr—B—N amorphous nitrided layer. Subsequently, in a second step, an AlGaN-based single crystal film is grown directly on the low-temperature buffer layer.

Abstract: A substrate for forming a semiconducting layer is provided to grow the semiconducting layer on a major surface thereof, wherein the substrate comprises a single crystal of a chemical formula of XB2 where X contains one of Ti and Zr and the major surface may preferably be substantially parallel to plane (0001) of the single crystal because the plane (0001) of the boride substrate is highly coherent to the lattices of GaN and AlN layers grown eptaxially on the substrate. The single crystal of the substrate may be a solid solution containing impurities of not more than 5%, wherein at least one of the impurities is one selected from Cr, Hf, V, Ta and Nb. Further, a semiconductor device includes the substrate of a single crystal of a chemical formula of XB2 and at least one semiconducting layer which is grown epitaxially on the substrate, the semiconducting layer including a nitride semiconductor of a chemical formula of ZN where Z is one of gallium, aluminum and indium and boron.

Abstract: A substrate for forming a semiconducting layeris provided to grow the semiconducting layer on a major surface thereof, wherein the substrate comprises a single crystal of a chemical formula of XB2 where X contains one of Ti and Zr and the major surface may preferably be substantially parallel to plane (0001) of the single crystal because the plane (0001) of the boride substrate is highly coherent to the lattices of GaN and AlN layers grown eptaxially on the substrate. The single crystal of the substrate may be a solid solution containing impurities of not more than 5%, wherein at least one of the impurities is one selected from Cr, Hf, V, Ta and Nb. Further, a semiconductor device includes the substrate of a single crystal of a chemical formula of XB2 and at least one semiconducting layer which is grown epitaxially on the substrate, the semiconducting layer including a nitride semiconductor of a chemical formula of ZN where Z is one of gallium, aluminum and indium and boron.