Patents by Inventor Jun Tsuiki
Jun Tsuiki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9325412Abstract: A transmission circuit of a transmission device transmits a signal to a reception circuit of a reception device via a plurality of signal paths included in a communication line. A first interface circuit is connected to the transmission circuit and one or more signal paths. A second interface circuit is connected to the transmission circuit and remaining signal paths expect for the one or more signal paths. A third interface circuit is connected to the reception circuit and the one or more signal paths. A fourth interface circuit is connected to the reception circuit and the remaining signal paths. An operation for transmitting and receiving the signal via the plurality of signal paths is changed to an operation for transmitting and receiving the signal via the remaining signal paths when the one or more signal paths enter a disconnected state.Type: GrantFiled: February 24, 2014Date of Patent: April 26, 2016Assignee: FUJITSU LIMITEDInventor: Jun Tsuiki
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Publication number: 20140286634Abstract: A transmission circuit of a transmission device transmits a signal to a reception circuit of a reception device via a plurality of signal paths included in a communication line. A first interface circuit is connected to the transmission circuit and one or more signal paths. A second interface circuit is connected to the transmission circuit and remaining signal paths expect for the one or more signal paths. A third interface circuit is connected to the reception circuit and the one or more signal paths. A fourth interface circuit is connected to the reception circuit and the remaining signal paths. An operation for transmitting and receiving the signal via the plurality of signal paths is changed to an operation for transmitting and receiving the signal via the remaining signal paths when the one or more signal paths enter a disconnected state.Type: ApplicationFiled: February 24, 2014Publication date: September 25, 2014Applicant: FUJITSU LIMITEDInventor: Jun TSUIKI
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Patent number: 8775679Abstract: Provided is a device for issuing a synchronization message in a large-scaled computing system including an interconnect and a plurality of computing devices that is connected to the interconnect. The interconnect includes a plurality of switches that is connected to each other. The device sends a synchronization message for synchronizing computing processes on the computing devices to all the computing devices at same timing via the switches that are directly connected to any of the computing devices by using a protocol for a general-purpose interconnect.Type: GrantFiled: November 2, 2009Date of Patent: July 8, 2014Assignee: Fujitsu LimitedInventors: Hiroyuki Oka, Jun Tsuiki
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Patent number: 8397094Abstract: A node-to-node synchronizing apparatus includes an information generating unit. Before receiving a synchronization request for synchronization, the information generating unit receives, from each process in each computing node, a mask generation request requesting to generate process location information (mask) indicating the location of processes that participate in synchronization. The information generating unit then automatically generates the process location information based on the mask generation request.Type: GrantFiled: July 29, 2009Date of Patent: March 12, 2013Assignee: Fujitsu LimitedInventors: Jun Tsuiki, Hiroyuki Oka
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Publication number: 20100121984Abstract: Provided is a device for issuing a synchronization message in a large-scaled computing system including an interconnect and a plurality of computing devices that is connected to the interconnect. The interconnect includes a plurality of switches that is connected to each other. The device sends a synchronization message for synchronizing computing processes on the computing devices to all the computing devices at same timing via the switches that are directly connected to any of the computing devices by using a protocol for a general-purpose interconnect.Type: ApplicationFiled: November 2, 2009Publication date: May 13, 2010Applicant: FUJITSU LIMITEDInventors: Hiroyuki Oka, Jun Tsuiki
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Publication number: 20100111115Abstract: A node-to-node synchronizing apparatus includes an information generating unit. Before receiving a synchronization request for synchronization, the information generating unit receives, from each process in each computing node, a mask generation request requesting to generate process location information (mask) indicating the location of processes that participate in synchronization. The information generating unit then automatically generates the process location information based on the mask generation request.Type: ApplicationFiled: July 29, 2009Publication date: May 6, 2010Applicant: Fujitsu LimitedInventors: Jun Tsuiki, Hiroyuki Oka
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Patent number: 7602868Abstract: The present invention provides an asynchronous transmission device and asynchronous transmission method which reduce the synchronization processing overhead.Type: GrantFiled: January 30, 2006Date of Patent: October 13, 2009Assignee: Fujitsu LimitedInventors: Jun Tsuiki, Masao Koyabu, Masahiro Kuramoto, Junichi Inagaki
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Patent number: 7555699Abstract: A method for address error check in a storage control circuit having a storage unit operable to store data in a storage area specified by an address encodes a first code assigned to the address with an even number of bits, encodes a second code assigned to the data written to the storage unit with an odd number of bits, generates a check code based on the first and second codes and stores the check code in the storage unit in correspondence with the data written to the storage unit, and conducts an error check based on data read from the storage unit, a check code corresponding to the data read, and a read address, thus detecting a multi-bit address error.Type: GrantFiled: September 28, 2005Date of Patent: June 30, 2009Assignee: Fujitsu LimitedInventors: Masahiro Kuramoto, Masao Koyabu, Jun Tsuiki, Junichi Inagaki
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Patent number: 7475170Abstract: The present invention is a data transfer device, which comprises an input/output reception buffer, an input/output transmission buffer, a write data buffer, a read data buffer, a control information table, a write data storing process section, a write data transmission section, a read data buffer storing process section, an input/output transmission buffer storing process section and a control section that executes an access control for controlling the access to the memory by the write data transmission section and the read data buffer storing process section based on a control information table; thereby, a configuration optimum for both protocols of the memory bus and the input/output bus is obtained and the out-of-order execution is also achievable.Type: GrantFiled: July 25, 2005Date of Patent: January 6, 2009Assignee: Fujitsu LimitedInventors: Junichi Inagaki, Masao Koyabu, Jun Tsuiki, Masahiro Kuramoto
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Patent number: 7353344Abstract: The present invention relates to a storage device which receives input of data of arbitrary data length, stores the data, and outputs the stored data in order of input. It provides a storage device capable of unloading data of arbitrary data length from data areas quickly. The storage device is equipped with a start position pointer which additionally stores the write position before the change each time a write position memorized by a write pointer is changed due to data input. When areas are freed, new read positions are determined based on saved write positions and the number of data items to be unloaded.Type: GrantFiled: October 26, 2004Date of Patent: April 1, 2008Assignee: Fujitsu LimitedInventor: Jun Tsuiki
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Publication number: 20070116165Abstract: The present invention provides an asynchronous transmission device and asynchronous transmission method which reduce the synchronization processing overhead.Type: ApplicationFiled: January 30, 2006Publication date: May 24, 2007Inventors: Jun Tsuiki, Masao Koyabu, Masahiro Kuramoto, Junichi Inagaki
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Publication number: 20060236205Abstract: A method for address error check in a storage control circuit having a storage unit operable to store data in a storage area specified by an address encodes a first code assigned to the address with an even number of bits, encodes a second code assigned to the data written to the storage unit with an odd number of bits, generates a check code based on the first and second codes and stores the check code in the storage unit in correspondence with the data written to the storage unit, and conducts an error check based on data read from the storage unit, a check code corresponding to the data read, and a read address, thus detecting a multi-bit address error.Type: ApplicationFiled: September 28, 2005Publication date: October 19, 2006Applicant: FUJITSU LIMITEDInventors: Masahiro Kuramoto, Masao Koyabu, Jun Tsuiki, Junichi Inagaki
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Publication number: 20060212661Abstract: The present invention is a data transfer device, which comprises an input/output reception buffer, an input/output transmission buffer, a write data buffer, a read data buffer, a control information table, a write data storing process section, a write data transmission section, a read data buffer storing process section, an input/output transmission buffer storing process section and a control section that executes an access control for controlling the access to the memory by the write data transmission section and the read data buffer storing process section based on a control information table; thereby, a configuration optimum for both protocols of the memory bus and the input/output bus is obtained and the out-of-order execution is also achievable.Type: ApplicationFiled: July 25, 2005Publication date: September 21, 2006Applicant: Fujitsu LimitedInventors: Junichi Inagaki, Masao Koyabu, Jun Tsuiki, Masahiro Kuramoto
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Publication number: 20060026368Abstract: The present invention relates to a storage device which receives input of data of arbitrary data length, stores the data, and outputs the stored data in order of input. It provides a storage device capable of unloading data of arbitrary data length from data areas quickly. The storage device is equipped with a start position pointer which additionally stores the write position before the change each time a write position memorized by a write pointer is changed due to data input. When areas are freed, new read positions are determined based on saved write positions and the number of data items to be unloaded.Type: ApplicationFiled: October 26, 2004Publication date: February 2, 2006Applicant: Fujitsu LimitedInventor: Jun Tsuiki
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Patent number: 6586983Abstract: A signal phase adjustment circuit to set an optimum phase by adjusting the difference in delay times between signal lines even when the distribution of the amount of phase modification that can be received normally is divided into a plurality of continuous regions. The amount of phase modification of the transmitted signal is allowed to fluctuate during one cycle of the operational frequency of the circuit. Determination of whether or not the reception signal during this interval can be received is continued, and the distribution of amount of phase modification that can be normally received is detected. The detected amount of phase modification defines continuous regions, and an optimum phase region is specified by selecting a region having a width of a specified value or more or the region having the greatest width. The optimum amount of sampling phase modification is determined from the upper and lower limit values of this region.Type: GrantFiled: March 22, 2002Date of Patent: July 1, 2003Assignee: Fujitsu LimitedInventors: Jun Tsuiki, Toshiyuki Shimizu
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Patent number: 6570424Abstract: A signal phase adjustment circuit to set an optimum phase by adjusting the difference in delay times between signal lines even when the distribution of the amount of phase modification that can be received normally is divided into a plurality of continuous regions. The amount of phase modification of the transmitted signal is allowed to fluctuate during one cycle of the operational frequency of the circuit. Determination of whether or not the reception signal during this interval can be received is continued, and the distribution of amount of phase modification that can be normally received is detected. The detected amount of phase modification defines continuous regions, and an optimum phase region is specified by selecting a region having a width of a specified value or more or the region having the greatest width. The optimum amount of sampling phase modification is determined from the upper and lower limit values of this region.Type: GrantFiled: March 22, 2002Date of Patent: May 27, 2003Assignee: Fujitsu LimitedInventors: Jun Tsuiki, Toshiyuki Shimizu
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Patent number: 6441664Abstract: A signal phase adjustment circuit to set an optimum phase by adjusting the difference in delay times between signal lines even when the distribution of the amount of phase modification that can be received normally is divided into a plurality of continuous regions. The amount of phase modification of the transmitted signal is allowed to fluctuate during one cycle of the operational frequency of the circuit. Determination of whether or not the reception signal during this interval can be received is continued, and the distribution of amount of phase modification that can be normally received is detected. The detected amount of phase modification defines continuous regions, and an optimum phase region is specified by selecting a region having a width of a specified value or more or the region having the greatest width. The optimum amount of sampling phase modification is determined from the upper and lower limit values of this region.Type: GrantFiled: December 11, 2000Date of Patent: August 27, 2002Assignee: Fujitsu LimitedInventors: Jun Tsuiki, Toshiyuki Shimizu
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Publication number: 20020097077Abstract: A signal phase adjustment circuit to set an optimum phase by adjusting the difference in delay times between signal lines even when the distribution of the amount of phase modification that can be received normally is divided into a plurality of continuous regions. The amount of phase modification of the transmitted signal is allowed to fluctuate during one cycle of the operational frequency of the circuit. Determination of whether or not the reception signal during this interval can be received is continued, and the distribution of amount of phase modification that can be normally received is detected. The detected amount of phase modification defines continuous regions, and an optimum phase region is specified by selecting a region having a width of a specified value or more or the region having the greatest width. The optimum amount of sampling phase modification is determined from the upper and lower limit values of this region.Type: ApplicationFiled: March 22, 2002Publication date: July 25, 2002Applicant: FUJITSU LIMITEDInventors: Jun Tsuiki, Toshiyuki Shimizu
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Publication number: 20020097078Abstract: A signal phase adjustment circuit to set an optimum phase by adjusting the difference in delay times between signal lines even when the distribution of the amount of phase modification that can be received normally is divided into a plurality of continuous regions. The amount of phase modification of the transmitted signal is allowed to fluctuate during one cycle of the operational frequency of the circuit. Determination of whether or not the reception signal during this interval can be received is continued, and the distribution of amount of phase modification that can be normally received is detected. The detected amount of phase modification defines continuous regions, and an optimum phase region is specified by selecting a region having a width of a specified value or more or the region having the greatest width. The optimum amount of sampling phase modification is determined from the upper and lower limit values of this region.Type: ApplicationFiled: March 22, 2002Publication date: July 25, 2002Applicant: FUJITSU LIMITEDInventors: Jun Tsuiki, Toshiyuki Shimizu
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Publication number: 20010050584Abstract: A signal phase adjustment circuit to set an optimum phase by adjusting the difference in delay times between signal lines even when the distribution of the amount of phase modification that can be received normally is divided into a plurality of continuous regions. The amount of phase modification of the transmitted signal is allowed to fluctuate during one cycle of the operational frequency of the circuit. Determination of whether or not the reception signal during this interval can be received is continued, and the distribution of amount of phase modification that can be normally received is detected. The detected amount of phase modification defines continuous regions, and an optimum phase region is specified by selecting a region having a width of a specified value or more or the region having the greatest width. The optimum amount of sampling phase modification is determined from the upper and lower limit values of this region.Type: ApplicationFiled: December 11, 2000Publication date: December 13, 2001Inventors: Jun Tsuiki, Toshiyuki Shimizu