Abstract: A wafer chuck for use in a semiconductor process chamber capable of producing an inert gas blanket positioned on the chuck from residual chemical vapor in the chamber is disclosed. A plurality of mounting pins for supporting a wafer is further provided in the upper surface for forming an inert gas into a cavity formed between the wafer and the upper surface of the chuck. A plurality of apertures in a sidewall of the body portion for flowing an inert gas into the lower chamber forming an inert gas blanket blocking a passageway between the upper and lower chambers, thus preventing the wafer from damage by residual chemical vapor in the lower chamber.

Abstract: A new method is provided for treating the surface of a layer of passivation where this layer of passivation comprises silicon dioxide or silicon nitride. An oxygen rich layer is created over the surface of the layer of passivation. Under the first embodiment of the invention a layer of silicon oxide is deposited over the surface of a substrate, a layer of plasma enhanced silicon nitride is deposited over the surface of the layer of silicon oxide, and a layer of oxynitride is deposited over the surface of the layer of plasma enhanced silicon nitride. Under the second embodiment of the invention a layer of silicon oxide is deposited over the surface of a substrate, a layer of silicon nitride is deposited over the surface of layer of silicon oxide. The surface of the layer of silicon nitride is oxidized by N2O or O2 plasma treatment.

Abstract: A wafer chuck for use in a semiconductor process chamber capable of producing an inert gas blanket positioned on the chuck from residual chemical vapor in the chamber is disclosed. A plurality of mounting pins for supporting a wafer is further provided in the upper surface for forming an inert gas into a cavity formed between the wafer and the upper surface of the chuck. A plurality of apertures in a sidewall of the body portion for flowing an inert gas into the lower chamber forming an inert gas blanket blocking a passageway between the upper and lower chambers, thus preventing the wafer from damage by residual chemical vapor in the lower chamber.

Abstract: A method for forming lining oxide in an opening for a shallow trench isolation and a method for forming a shallow trench isolation incorporating a lining oxide layer are described. In the method for forming lining oxide, a silicon substrate is first provided, followed by a process of forming a pad oxide layer and a silicon nitride mask sequentially on top of the silicon substrate. A trench opening is then patterned and formed in the silicon substrate for the shallow trench isolation. The silicon substrate is then annealed at a temperature of at least 1,000° C. in a furnace in an environment that contains not more than 10 vol. % oxygen. A lining oxide layer is formed in the same furnace used for annealing the structure of the trench opening in the silicon substrate.