Abstract: A gear-double ring-hydraulic hybrid transmission device includes an input mechanism, a double ring series transmission mechanism, a hydraulic transmission mechanism, an output member, a front planetary gear mechanism, a middle planetary gear mechanism, a rear planetary gear mechanism, a clutch assembly, and a brake assembly. An output of the double ring series transmission mechanism is connected to the middle planetary gear mechanism. The clutch assembly connects the input mechanism to the double ring series transmission mechanism, the hydraulic transmission mechanism, and the front planetary gear mechanism, connects an output of the hydraulic transmission mechanism to the middle planetary gear mechanism, and connects an output of the rear planetary gear mechanism to the output member. The clutch assembly and the brake assembly provide a continuous transmission ratio between the input mechanism and the output member.

Abstract: An apparatus comprises one or more non-clock and data recovery (CDR) components on a substrate, a signal generator on the substrate and coupled to at least one of the one or more non-CDR components, and a CDR component on the substrate and coupled to the one or more non-CDR components, wherein the CDR component is configured to recover clock data from a received signal by the CDR component, and configured to determine a signal based on the received signal and the clock data.

Abstract: An apparatus comprises one or more non-clock and data recovery (CDR) components on a substrate, a signal generator on the substrate and coupled to at least one of the one or more non-CDR components, and a CDR component on the substrate and coupled to the one or more non-CDR components, wherein the CDR component is configured to recover clock data from a received signal by the CDR component, and configured to determine a signal based on the received signal and the clock data.

Abstract: An apparatus comprises a plurality of sampling circuits configured to receive a non-Non Return to Zero (non-NRZ) data signal; and a control circuit coupled to the plurality of sampling circuits, wherein the control circuit is configured to provide one or more control signals indicating whether to decrease or increase a frequency of a clock signal associated with the non-NRZ data signal based on the non-NRZ data signal.

Abstract: An apparatus comprises a plurality of sampling circuits configured to receive a non-Non Return to Zero (non-NRZ) data signal; and a control circuit coupled to the plurality of sampling circuits, wherein the control circuit is configured to provide one or more control signals indicating whether to decrease or increase a frequency of a clock signal associated with the non-NRZ data signal based on the non-NRZ data signal.

Abstract: An apparatus comprises a plurality of sampling circuits configured to receive a non-Non Return to Zero (non-NRZ) data signal; and a control circuit coupled to the plurality of sampling circuits, wherein the control circuit is configured to provide one or more control signals indicating whether to decrease or increase a frequency of a clock signal associated with the non-NRZ data signal based on the non-NRZ data signal.

Abstract: An apparatus comprises a plurality of sampling circuits configured to receive a non-Non Return to Zero (non-NRZ) data signal; and a control circuit coupled to the plurality of sampling circuits, wherein the control circuit is configured to provide one or more control signals indicating whether to decrease or increase a frequency of a clock signal associated with the non-NRZ data signal based on the non-NRZ data signal.

Abstract: An apparatus comprises a plurality of sampling circuits configured to receive a non-Non Return to Zero (non-NRZ) data signal; and a control circuit coupled to the plurality of sampling circuits, wherein the control circuit is configured to provide one or more control signals indicating whether to decrease or increase a frequency of a clock signal associated with the non-NRZ data signal based on the non-NRZ data signal.

Abstract: An apparatus comprises a plurality of sampling circuits configured to receive a non-Non Return to Zero (non-NRZ) data signal; and a control circuit coupled to the plurality of sampling circuits, wherein the control circuit is configured to provide one or more control signals indicating whether to decrease or increase a frequency of a clock signal associated with the non-NRZ data signal based on the non-NRZ data signal.

Abstract: An apparatus comprises a plurality of sampling circuits configured to receive a non-Non Return to Zero (non-NRZ) data signal; and a control circuit coupled to the plurality of sampling circuits, wherein the control circuit is configured to provide one or more control signals indicating whether to decrease or increase a frequency of a clock signal associated with the non-NRZ data signal based on the non-NRZ data signal.

Abstract: An apparatus comprises a plurality of sampling circuits configured to receive a non-Non Return to Zero (non-NRZ) data signal; and a control circuit coupled to the plurality of sampling circuits, wherein the control circuit is configured to provide one or more control signals indicating whether to decrease or increase a frequency of a clock signal associated with the non-NRZ data signal based on the non-NRZ data signal.

Abstract: An apparatus comprises a plurality of sampling circuits configured to receive a non-Non Return to Zero (non-NRZ) data signal; and a control circuit coupled to the plurality of sampling circuits, wherein the control circuit is configured to provide one or more control signals indicating whether to decrease or increase a frequency of a clock signal associated with the non-NRZ data signal based on the non-NRZ data signal.

Abstract: An apparatus comprises a plurality of sampling circuits configured to receive a non-Non Return to Zero (non-NRZ) data signal; and a control circuit coupled to the plurality of sampling circuits, wherein the control circuit is configured to provide one or more control signals indicating whether to decrease or increase a frequency of a clock signal associated with the non-NRZ data signal based on the non-NRZ data signal.

Abstract: An apparatus comprises a plurality of sampling circuits configured to receive a non-Non Return to Zero (non-NRZ) data signal; and a control circuit coupled to the plurality of sampling circuits, wherein the control circuit is configured to provide one or more control signals indicating whether to decrease or increase a frequency of a clock signal associated with the non-NRZ data signal based on the non-NRZ data signal.

Abstract: An apparatus comprises a plurality of sampling circuits configured to receive a non-Non Return to Zero (non-NRZ) data signal; and a control circuit coupled to the plurality of sampling circuits, wherein the control circuit is configured to provide one or more control signals indicating whether to decrease or increase a frequency of a clock signal associated with the non-NRZ data signal based on the non-NRZ data signal.

Abstract: The present invention discloses a PLL, a lock detector thereof and a lock detection method. The lock detector includes: a first detecting unit, adapted to compare a counting value of a reference clock signal with a counting value of a feedback clock signal every first interval and output a valid first prelock signal when the counting value of the reference clock signal is equal to the counting value of the feedback clock signal; a second detecting unit, adapted to output a valid second prelock signal when the counting value of the reference clock signal is equal to the counting value of the feedback clock signal during a second interval which is at least two times higher than the first interval; a third detecting unit, adapted to output a valid lock signal if the first prelock signal output from the first detecting unit every first interval is valid and the second prelock signal output from the second detecting unit is valid during the second interval.

Abstract: The present invention discloses a PLL, a lock detector thereof and a lock detection method. The lock detector includes: a first detecting unit, adapted to compare a counting value of a reference clock signal with a counting value of a feedback clock signal every first interval and output a valid first prelock signal when the counting value of the reference clock signal is equal to the counting value of the feedback clock signal; a second detecting unit, adapted to output a valid second prelock signal when the counting value of the reference clock signal is equal to the counting value of the feedback clock signal during a second interval which is at least two times higher than the first interval; a third detecting unit, adapted to output a valid lock signal if the first prelock signal output from the first detecting unit every first interval is valid and the second prelock signal output from the second detecting unit is valid during the second interval.