Abstract: Disclosed is the present disclosure relates to a marine cable for offshore wind power having an improved water-tree property. More particularly, it relates to a marine cable for offshore wind power, which may effectively suppress formation of water trees caused by diffusion of moisture, having penetrated into cores of the cable, in insulating layers so as to improve dielectric strength and consequently secure a long lifespan.

Abstract: Provided herein is technology relating to collecting and containing samples and particularly, but not exclusively, to technology for collecting and containing a stool specimen. The technology provides a device for collecting and containing a stool specimen, the device comprising ergonomic features optimized for a geriatric user. The technology also provides an enclosing holder for securing the ergonomic stool specimen container in a leak-proof manner e.g., during mechanical shaking.

Abstract: Disclosed herein is a method of supporting implant surgery in a server, which includes obtaining a subject's oral CT image scanned with a guide model inserted into an oral cavity of the subject, the guide model being manufactured to a certain standard to group human teeth in any range so that the teeth belong to at least one group and to cover a tooth position of a corresponding group, the guide model including a marker made of a radiopaque or radiation semipermeable material, loading a library as information about the standard of the guide model, identifying the marker in the oral CT image, and generating a library matching CT image by matching the oral CT image with the library based on the marker included in the library and the marker identified in the oral CT image, and planning implant surgery of the subject using the library matching CT image.

Abstract: A test structure on a wafer is provided. The test structure includes a plurality of cells under test, a first output pad and a second output pad coupled to different cells, a plurality of first input pads, and a plurality of second input pads. The cells are arranged in rows and columns of a test array. Each of the first input pads is coupled to the cells in respective column of the test array. Each of the second input pads is coupled to the cells in respective row of the test array. A first voltage is applied to one of the first input pads and a second voltage is applied to one of the second input pads to turn on a cell, and a current flowing through the turned-on cell is measured.

Abstract: Discussed is a battery module that may include a battery cell stack including a plurality of battery cells arranged along a first direction; side plates covering each of opposite side surfaces of the battery cell stack along the first direction, respectively; a busbar frame covering one surface of the battery cell stack in a direction in which electrode leads of the plurality of battery cells protrude; and a disc spring part located on an outside of a side plate of the side plates. The disc spring part is compressed in a direction parallel to the first direction.

Abstract: A battery pack includes a plurality of battery cells; a housing accommodating the plurality of battery cells; a plurality of bus bars electrically connecting the plurality of battery cells; and a first welding portion for coupling a first electrode terminal provided in each of the plurality of battery cells to the bus bar and a second welding portion for coupling a second electrode terminal provided in each of the plurality of battery cells to the bus bar. At least one of the first welding portion and the second welding portion includes a region in which a laser welding line formed on the bus bar proceeds in a direction opposite to an extension direction of the welding portion.

Abstract: A method includes forming a first fin and a second fin protruding from a frontside of a substrate, forming a gate stack over the first and second fins, forming a dielectric feature dividing the gate stack into a first segment engaging the first fin and a second segment engaging the second fin, and growing a first epitaxial feature on the first fin and a second epitaxial feature on the second fin. The dielectric feature is disposed between the first and second epitaxial features. The method also includes performing an etching process on a backside of the substrate to form a backside trench, and forming a backside via in the backside trench. The backside trench exposes the dielectric feature and the first and second epitaxial features. The backside via straddles the dielectric feature and is in electrical connection with the first and second epitaxial features.

Abstract: Various embodiments of the present disclosure are directed towards a method for forming an integrated chip (IC). The method includes forming a first fin of semiconductor material and a second fin of semiconductor material within a semiconductor substrate. A gate structure is formed over the first fin and source/drain regions are formed on or within the first fin. The source/drain regions are formed on opposite sides of the gate structure. One or more pick-up regions are formed on or within the second fin. The source/drain regions respectively have a first width measured along a first direction parallel to a long axis of the first fin and the one or more pick-up regions respectively have a second width measured along the first direction. The second width is larger than the first width.

Abstract: A prepreg and uses thereof are provided. The prepreg includes an organic fiber woven fabric impregnated or coated with a thermally curable resin composition, wherein the thermally curable resin composition includes: (A) a polyphenylene ether resin having an unsaturated functional group; (B) a polyfunctional vinyl aromatic copolymer; and (C) a compound having the structure of formula (I), wherein, in formula (I), X is a C1-C10 linear or branched alkylene; and the polyfunctional vinyl aromatic copolymer is prepared by copolymerizing one or more divinyl aromatic compounds with one or more monovinyl aromatic compounds.

Abstract: A flash memory storage management method includes: providing a flash memory module including single-level-cell (SLC) blocks and at least one multiple-level-cell block such as MLC block, TLC block, or QLC block; classifying data to be programmed into groups of data; respectively executing SLC programing and RAID-like error code encoding to generate corresponding parity check codes, to program the groups of data and corresponding parity check codes to the SLC blocks; when completing program of the SLC blocks, performing an internal copy to program the at least one multiple-level-cell block by sequentially reading and writing the groups of data and corresponding parity check codes from the SLC blocks to the multiple-level-cell block according to a storage order of the SLC blocks.

Abstract: A semiconductor device according to the present disclosure includes a gate extension structure, a first source/drain feature and a second source/drain feature, a vertical stack of channel members extending between the first source/drain feature and the second source/drain feature along a direction, and a gate structure wrapping around each of the vertical stack of channel members. The gate extension structure is in direct contact with the first source/drain feature.

Abstract: A battery module includes battery cells stacked along one direction; a heat conducting member that transfers heat generated from the battery cells to the outside; and an insulating member surrounding the heat conducting member. At least one or more of the battery cells form a battery cell group, and at least one battery cell group is stacked to form a battery cell stack.

Abstract: The present invention relates to a composition for preventing or treating transplantation rejection or a transplantation rejection disease, comprising a novel compound and a calcineurin inhibitor. A co-administration of the present invention 1) reduces the activity of pathogenic Th1 cells or Th17 cells, 2) increases the activity of Treg cells, 3) has an inhibitory effect against side effects, such as tissue damage, occurring in the sole administration thereof, 4) inhibits various pathogenic pathways, 5) inhibits the cell death of inflammatory cells, and 6) increases the activity of mitochondria, in an in vivo or in vitro allogenic model, a transplantation rejection disease model, a skin transplantation model, and a liver-transplanted patient, and thus inhibits transplantation rejection along with mitigating side effects possibly occurring in the administration of a conventional immunosuppressant alone.

Abstract: In an embodiment, a system, includes: a first pressurized load port interfaced with a workstation body; a second pressurized load port interfaced with the workstation body; the workstation body maintained at a set pressure level, wherein the workstation body comprises an internal material handling system configured to move a semiconductor workpiece within the workstation body between the first and second pressurized load ports at the set pressure level; a first modular tool interfaced with the first pressurized load port, wherein the first modular tool is configured to process the semiconductor workpiece; and a second modular tool interfaced with the second pressurized load port, wherein the second modular tool is configured to inspect the semiconductor workpiece processed by the first modular tool.

Abstract: An outlier IC detection method includes acquiring first measured data of a first IC set, training the first measured data for establishing a training model, acquiring second measured data of a second IC set, generating predicted data of the second IC set by using the training model according to the second measured data, generating a bivariate dataset distribution of the second IC set according to the predicted data and the second measured data, acquiring a predetermined Mahalanobis distance on the bivariate dataset distribution of the second IC set, and identifying at least one outlier IC from the second IC set when at least one position of the at least one outlier IC on the bivariate dataset distribution is outside a range of the predetermined Mahalanobis distance.

Abstract: Provided is a pharmaceutical composition including gastrodin and a use thereof for the prevention or the treatment of amyotrophic lateral sclerosis. The pharmaceutical composition is effective in reducing neuronal axon degeneration and neurofibromin accumulation, improving symptoms of amyotrophic lateral sclerosis and extending life of patients of amyotrophic lateral sclerosis.

Abstract: In an embodiment, a method includes: forming a first inter-metal dielectric (IMD) layer over a semiconductor substrate; forming a bottom electrode layer over the first IMD layer; forming a magnetic tunnel junction (MTJ) film stack over the bottom electrode layer; forming a first top electrode layer over the MTJ film stack; forming a protective mask covering a first region of the first top electrode layer, a second region of the first top electrode layer being uncovered by the protective mask; forming a second top electrode layer over the protective mask and the first top electrode layer; and patterning the second top electrode layer, the first top electrode layer, the MTJ film stack, the bottom electrode layer, and the first IMD layer with an ion beam etching (IBE) process to form a MRAM cell, where the protective mask is etched during the IBE process.

Abstract: A thin film transistor includes an active layer located over a substrate, a first gate stack including a stack of a first gate dielectric and a first gate electrode and located on a first surface of the active layer, a pair of first contact electrodes contacting peripheral portions of the first surface of the active layer and laterally spaced from each other along a first horizontal direction by the first gate electrode, a second contact electrode contacting a second surface of the active layer that is vertically spaced from the first surface of the active layer, and a pair of second gate stacks including a respective stack of a second gate dielectric and a second gate electrode and located on a respective peripheral portion of a second surface of the active layer.

Abstract: A display device comprises a display panel substrate and a glass substrate over said display panel substrate, wherein said display panel substrate comprises multiple contact pads, a display area, a first boundary, a second boundary, a third boundary and a fourth boundary, wherein said display area comprises a first edge, a second edge, a third edge and a fourth edge, wherein said first boundary is parallel to said third boundary and said first and third edges, wherein said second boundary is parallel to said fourth boundary and said second and fourth edges, wherein a first least distance between said first boundary and said first edge, wherein a second least distance between said second boundary and said second edge, a third least distance between said third boundary and said third edge, a fourth distance between said fourth boundary and said fourth edge, and wherein said first, second, third and fourth least distances are smaller than 100 micrometers, and wherein said glass substrate comprising multiple meta