Patents by Inventor JUNG-AN CHENG
JUNG-AN CHENG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11996483Abstract: The present disclosure provides a semiconductor device that includes a semiconductor fin disposed over a substrate, an isolation structure at least partially surrounding the fin, an epitaxial source/drain (S/D) feature disposed over the semiconductor fin, where an extended portion of the epitaxial S/D feature extends over the isolation structure, and a silicide layer disposed on the epitaxial S/D feature, where the silicide layer covers top, bottom, sidewall, front, and back surfaces of the extended portion of the S/D feature.Type: GrantFiled: December 14, 2022Date of Patent: May 28, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Pei-Hsun Wang, Chih-Chao Chou, Shih-Cheng Chen, Jung-Hung Chang, Jui-Chien Huang, Chun-Hsiung Lin, Chih-Hao Wang
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Patent number: 11996482Abstract: A device includes a semiconductor substrate, a channel layer, a gate structure, source/drain epitaxial structures, and a dielectric isolation layer. The channel layer is over the semiconductor substrate. The gate structure is over the semiconductor substrate and surrounds the channel layer. The source/drain epitaxial structures are connected to the channel layer and arranged in a first direction. The dielectric isolation layer is between the gate structure and the semiconductor substrate. The dielectric isolation layer is wider than the gate structure but narrower than the channel layer in the first direction.Type: GrantFiled: March 13, 2023Date of Patent: May 28, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Zhi-Chang Lin, Shih-Cheng Chen, Jung-Hung Chang, Lo-Heng Chang, Chien-Ning Yao
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Publication number: 20240170556Abstract: A method for forming a semiconductor structure is provided. The method includes forming a spacer layer along a first fin structure and a second fin structure, etching a first portion of the spacer layer and the first fin structure to form first fin spacers and a first recess between the first fin spacers, etching a second portion of the spacer layer and the second fin structure to form second fin spacers and a second recess between the second fin spacers, and forming a first source/drain feature in the first recess and a second source/drain feature in the second recess. The second fin structure is wider than the first fin structure. The first fin spacers have a first height, and the second fin spacers have a second height that is greater than the first height.Type: ApplicationFiled: February 20, 2023Publication date: May 23, 2024Inventors: Shih-Cheng CHEN, Zhi-Chang LIN, Jung-Hung CHANG, Chien-Ning YAO, Tsung-Han CHUANG, Kuo-Cheng CHIANG
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Publication number: 20240170337Abstract: The present disclosure describes a semiconductor structure with a dielectric liner. The semiconductor structure includes a substrate and a fin structure on the substrate. The fin structure includes a stacked fin structure, a fin bottom portion below the stacked fin structure, and an isolation layer between the stacked fin structure and the bottom fin portion. The semiconductor structure further includes a dielectric liner in contact with an end of the stacked fin structure and a spacer structure in contact with the dielectric liner.Type: ApplicationFiled: January 30, 2024Publication date: May 23, 2024Applicant: Taiwan Semiconductor Manufacturing Company Ltd.Inventors: Zhi-Chang LIN, Shih-Cheng CHEN, Kuo-Cheng CHIANG, Kuan-Ting PAN, Jung-Hung CHANG, Lo-Heng CHANG, Chien Ning YAO
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Patent number: 11990440Abstract: A structure and a formation method of a semiconductor device are provided. The semiconductor device structure includes a semiconductor substrate and an interconnection structure over the semiconductor substrate. The semiconductor device structure also includes a first conductive pillar over the interconnection structure. The first conductive pillar has a first protruding portion extending towards the semiconductor substrate from a lower surface of the first conductive pillar. The semiconductor device structure further includes a second conductive pillar over the interconnection structure. The second conductive pillar has a second protruding portion extending towards the semiconductor substrate from a lower surface of the second conductive pillar. The first conductive pillar is closer to a center point of the semiconductor substrate than the second conductive pillar. A bottom of the second protruding portion is wider than a bottom of the first protruding portion.Type: GrantFiled: August 27, 2021Date of Patent: May 21, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Hui-Min Huang, Ming-Da Cheng, Wei-Hung Lin, Chang-Jung Hsueh, Kai-Jun Zhan, Yung-Sheng Lin
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Patent number: 11987883Abstract: A powder atomic layer deposition apparatus for blowing powders is disclosed. The powder atomic layer deposition apparatus includes a vacuum chamber, a shaft sealing device, and a driving unit. The driving unit drives the vacuum chamber to rotate through the shaft sealing device. The shaft sealing device includes an outer tube and an inner tube, wherein the inner tube is arranged in an accommodating space of the outer tube. At least one air extraction line and at least one air intake line are located in the inner tube, wherein the air intake line extends from the inner tube into a reaction space within the vacuum chamber, and is used to transport the a non-reactive gas to the reaction space to blow the powders around in the reaction space.Type: GrantFiled: May 30, 2021Date of Patent: May 21, 2024Assignee: SKY TECH INC.Inventors: Jing-Cheng Lin, Jung-Hua Chang, Chia-Cheng Ku
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Publication number: 20240162227Abstract: A semiconductor device structure, along with methods of forming such, are described. The method includes forming a first dielectric feature between first and the second fin structures, wherein each first and second fin structure includes first semiconductor layers and second semiconductor layers alternatingly stacked and in contact with the first dielectric layer. The method also includes removing the second semiconductor layers so that the first semiconductor layers of the first and second fin structures extend laterally from a first side and a second side of the first dielectric feature, respectively, trimming the first dielectric feature so that the first dielectric feature has a reduced thickness on both first and the second sides, and forming a gate electrode layer to surround each of the first semiconductor layers of the first and second fin structures.Type: ApplicationFiled: November 19, 2023Publication date: May 16, 2024Inventors: Guan-Lin CHEN, Kuo-Cheng CHIANG, Shi Ning JU, Jung-Chien CHENG, Chih-Hao WANG, Kuan-Lun CHENG
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Patent number: 11985647Abstract: Methods, systems, and devices for sidelink groupcast communications are described. A user equipment (UE) may transmit a beam training request to a base station to determine beams for use with other UEs in a sidelink groupcast communications group. The base station may receive the beam training request, identify wireless resources that a group of UEs may use to perform beam training, and may transmit a beam training grant to each UE of the group of UEs. The UE may transmit a number of training beams using the wireless resources provided in the beam training grant, and the other UEs may measure received signals on the wireless resources to identify one or more beams. Each UE may provide a beam training report to the base station. The base station, based on the beam training reports, may determine beams and resources for use in the groupcast sidelink communications.Type: GrantFiled: October 15, 2020Date of Patent: May 14, 2024Assignee: QUALCOMM IncorporatedInventors: Jung Ho Ryu, Sony Akkarakaran, Tao Luo, Kapil Gulati, Hong Cheng, Juan Montojo, Mahmoud Taherzadeh Boroujeni, Junyi Li
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Patent number: 11983052Abstract: A display device and a bezel thereof are provided. The display device includes a display panel and a bezel. The display panel has a first surface and a second surface. The first surface includes at least one pixel pad section, and the second surface includes at least one circuit pad section. The bezel includes a first surface connecting portion, a second surface connecting portion and at least one conductive wire. The edge of the display panel having the pixel pad section and the circuit pad section is accommodated between the first surface connecting portion and the second surface connecting portion. Each conductive wire has a first end and a second end. The first end is disposed on the first surface connecting portion and the second end is disposed on the second surface connecting portion. The part of the first connecting portion having the first end corresponds to the pixel pad section, and the part of the second connecting portion having the second end corresponds to the circuit pad section.Type: GrantFiled: May 28, 2021Date of Patent: May 14, 2024Assignee: AU OPTRONICS CORPORATIONInventors: Yi-Fan Chen, Che-Chia Chang, Shang-Jie Wu, Yu-Chieh Kuo, Yi-Jung Chen, Yu-Hsun Chiu, Mei-Yi Li, He-Yi Cheng
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Patent number: 11984361Abstract: A semiconductor device includes a substrate, a plurality of nanosheets, a plurality of source/drain (S/D) features, and a gate stack. The substrate includes a first fin and a second fin. The first fin has a first width less than a second width of the second fin. The plurality of nanosheets is disposed on the first fin and the second fin. The plurality of source/drain (S/D) features are located on the first fin and the second fin and abutting the plurality of nanosheets. A bottom surface of the plurality of source/drain (S/D) features on the first fin is equal to or lower than a bottom surface of the plurality of source/drain (S/D) features on the second fin. The gate stack wraps each of the plurality of nanosheets.Type: GrantFiled: February 10, 2023Date of Patent: May 14, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Lo-Heng Chang, Chih-Hao Wang, Kuo-Cheng Chiang, Jung-Hung Chang, Pei-Hsun Wang
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Publication number: 20240153958Abstract: A semiconductor device structure, along with methods of forming such, are described. The structure includes a plurality of semiconductor layers having a first group of semiconductor layers, a second group of semiconductor layers disposed over and aligned with the first group of semiconductor layers, and a third group of semiconductor layers disposed over and aligned with the second group of semiconductor layers. The structure further includes a first source/drain epitaxial feature in contact with a first number of semiconductor layers of the first group of semiconductor layers and a second source/drain epitaxial feature in contact with a second number of semiconductor layers of the third group of semiconductor layers. The first number of semiconductor layers of the first group of semiconductor layers is different from the second number of semiconductor layers of the third group of semiconductor layers.Type: ApplicationFiled: January 7, 2024Publication date: May 9, 2024Inventors: Jung-Hung CHANG, Zhi-Chang LIN, Shih-Cheng CHEN, Chien Ning YAO, Kuo-Cheng CHIANG, Chih-Hao WANG
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Publication number: 20240138771Abstract: A pulse manifestation determining method is provided. The pulse manifestation method includes following steps. A pulse signal for determination is obtained. A valid range of the pulse signal for determination is determined through identifying a reverse pulse. A pulse manifestation is determined based on the valid range.Type: ApplicationFiled: July 31, 2023Publication date: May 2, 2024Applicant: AUO CorporationInventors: Chien Cheng Wang, Jung-Teng Pan, Chin-Tang Chuang
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Publication number: 20240145540Abstract: A semiconductor device includes a first active region, a second active region and a dielectric wall. The second active region disposed adjacent to the first active region, and there is a first space between the first active region and the second active region. The dielectric wall is formed within the first space and has a first sidewall and a second sidewall opposite to the first sidewall. The first sidewall and the second sidewall opposite to the first sidewall continuously extend along a plane.Type: ApplicationFiled: January 20, 2023Publication date: May 2, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Shi Ning JU, Kuo-Cheng CHIANG, Guan-Lin CHEN, Jung-Chien CHENG, Chih-Hao WANG
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Patent number: 11967594Abstract: A semiconductor device structure, along with methods of forming such, are described. The structure includes a stack of semiconductor layers spaced apart from and aligned with each other, a first source/drain epitaxial feature in contact with a first one or more semiconductor layers of the stack of semiconductor layers, and a second source/drain epitaxial feature disposed over the first source/drain epitaxial feature. The second source/drain epitaxial feature is in contact with a second one or more semiconductor layers of the stack of semiconductor layers. The structure further includes a first dielectric material disposed between the first source/drain epitaxial feature and the second source/drain epitaxial feature and a first liner disposed between the first source/drain epitaxial feature and the second source/drain epitaxial feature. The first liner is in contact with the first source/drain epitaxial feature and the first dielectric material.Type: GrantFiled: August 10, 2022Date of Patent: April 23, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Shih-Cheng Chen, Zhi-Chang Lin, Jung-Hung Chang, Lo Heng Chang, Chien Ning Yao, Kuo-Cheng Chiang, Chih-Hao Wang
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Publication number: 20240126821Abstract: Techniques for providing suggested content is described. For example, a social networking system may receive, from an account of a social networking system, an indication of a selection of a first content item. The social networking system may determine that the first content item is associated with a first topic and may receive a request from the account to access a second content item associated with the first topic. The social networking system may then cause presentation of the second content item and may determine that the request meets or exceeds a threshold number of requests for content items associated with the first topic. Based on determining that the request meets or exceeds the threshold, the social networking system may cause presentation of a suggested content item associated with a second topic.Type: ApplicationFiled: October 17, 2022Publication date: April 18, 2024Inventors: Han Ren, Shruti Bhutada, Jus-Tin Cheng, Ellen Yutong Lu, Rehman Khan, Jonathan Eusung Kim, Shilpa Mody, Woo Jung Oh, Kyle Yank Zhu, Gargi Apte, Moira Kathleen Ballantyne Burke
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Publication number: 20240128232Abstract: A semiconductor package includes a first semiconductor die, an encapsulant, a high-modulus dielectric layer and a redistribution structure. The first semiconductor die includes a conductive post in a protective layer. The encapsulant encapsulates the first semiconductor die, wherein the encapsulant is made of a first material. The high-modulus dielectric layer extends on the encapsulant and the protective layer, wherein the high-modulus dielectric layer is made of a second material. The redistribution structure extends on the high-modulus dielectric layer, wherein the redistribution structure includes a redistribution dielectric layer, and the redistribution dielectric layer is made of a third material. The protective layer is made of a fourth material, and a ratio of a Young's modulus of the second material to a Young's modulus of the fourth material is at least 1.5.Type: ApplicationFiled: December 28, 2023Publication date: April 18, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Tsung-Ding Wang, Yen-Fu Su, Hao-Cheng Hou, Jung-Wei Cheng, Chien-Hsun Lee, Hsin-Yu Pan
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Publication number: 20240128219Abstract: A semiconductor die including mechanical-stress-resistant bump structures is provided. The semiconductor die includes dielectric material layers embedding metal interconnect structures, a connection pad-and-via structure, and a bump structure including a bump via portion and a bonding bump portion. The entirety of a bottom surface of the bump via portion is located within an area of a horizontal top surface of a pad portion of the connection pad-and-via structure.Type: ApplicationFiled: December 6, 2023Publication date: April 18, 2024Inventors: Hui-Min Huang, Wei-Hung Lin, Kai Jun Zhan, Chang-Jung Hsueh, Wan-Yu Chiang, Ming-Da Cheng
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Publication number: 20240128148Abstract: A method includes attaching a package component to a package substrate, the package component includes: an interposer disposed over the package substrate; a first die disposed along the interposer; and a second die disposed along the interposer, the second die being laterally adjacent the first die; attaching a first thermal interface material to the first die, the first thermal interface material being composed of a first material; attaching a second thermal interface material to the second die, the second thermal interface material being composed of a second material different from the first material; and attaching a lid assembly to the package substrate, the lid assembly being further attached to the first thermal interface material and the second thermal interface material.Type: ApplicationFiled: January 6, 2023Publication date: April 18, 2024Inventors: Chang-Jung Hsueh, Po-Yao Lin, Hui-Min Huang, Ming-Da Cheng, Kathy Yan
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Patent number: 11959960Abstract: A voltage tracking circuit includes first, second, third and fourth transistors. The first transistor is in a first well, and includes a first gate, a first drain and a first source coupled to a first voltage supply. The second transistor includes a second gate, a second drain and a second source. The second source is coupled to the first drain. The second gate is coupled to the first gate and a pad voltage terminal. The second body terminal is coupled to a first node. The third transistor includes a third gate, a third drain and a third source. The fourth transistor includes a fourth gate, a fourth drain and a fourth source. The fourth drain is coupled to the third source. The fourth source is coupled to the pad voltage terminal. The second transistor is in a second well different from the first well, and is separated from the first well in a first direction.Type: GrantFiled: May 1, 2023Date of Patent: April 16, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Hsiang-Hui Cheng, Chia-Jung Chang
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Patent number: D1024051Type: GrantFiled: August 10, 2021Date of Patent: April 23, 2024Assignee: Acer IncorporatedInventors: Hui-Jung Huang, Hong-Kuan Li, I-Lun Li, Ling-Mei Kuo, Kuan-Ju Chen, Fang-Ying Huang, Kai-Hung Huang, Szu-Wei Yang, Kai-Teng Cheng