Patents by Inventor Jung Cheng

Jung Cheng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240313116
    Abstract: A method includes providing a semiconductor structure including a first semiconductor substrate, an insulator layer over the first semiconductor substrate, and a second semiconductor substrate over the insulator layer; patterning the second semiconductor substrate to form a top fin portion over the insulator layer; conformally depositing a protection layer to cover the top fin portion, wherein a first portion of the protection layer is in contact with a top surface of the insulator layer; etching the protection layer to remove a second portion of the protection layer directly over the top fin portion while a third portion of the protection layer still covers a sidewall of the top fin portion; etching the insulator layer by using the third portion of the protection layer as an etch mask; and after etching the insulator layer, removing the third portion of the protection layer.
    Type: Application
    Filed: May 21, 2024
    Publication date: September 19, 2024
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shu-Hao KUO, Jung-Hao CHANG, Chao-Hsien HUANG, Li-Te LIN, Kuo-Cheng CHING
  • Publication number: 20240313048
    Abstract: A semiconductor device structure and a formation method are provided. The method includes forming a channel structure over a substrate and forming a protective spacer over sidewalls of the channel structure. The method also includes forming an insulating wall adjacent to an end of the channel structure. The method further includes removing the protective spacer to expose the channel structure. In addition, the method includes forming a metal gate stack surrounding an intermediate portion of the channel structure.
    Type: Application
    Filed: March 16, 2023
    Publication date: September 19, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuo-Cheng CHIANG, Guan-Lin CHEN, Shi-Ning JU, Jung-Chien CHENG, Chih-Hao WANG
  • Publication number: 20240313118
    Abstract: The present disclosure provides a semiconductor device that includes a semiconductor fin disposed over a substrate, an isolation structure at least partially surrounding the fin, an epitaxial source/drain (S/D) feature disposed over the semiconductor fin, where an extended portion of the epitaxial S/D feature extends over the isolation structure, and a silicide layer disposed on the epitaxial S/D feature, where the silicide layer covers top, bottom, sidewall, front, and back surfaces of the extended portion of the S/D feature.
    Type: Application
    Filed: May 24, 2024
    Publication date: September 19, 2024
    Inventors: Pei-Hsun Wang, Chih-Chao Chou, Shih-Cheng Chen, Jung-Hung Chang, Jui-Chien Huang, Chun-Hsiung Lin, Chih-Hao Wang
  • Patent number: 12094880
    Abstract: An integrated circuit includes a first diffusion area for a first type transistor. The first type transistor includes a first drain region and a first source region. A second diffusion area for a second type transistor is separated from the first diffusion area. The second type transistor includes a second drain region and a second source region. A gate electrode continuously extends across the first diffusion area and the second diffusion area in a routing direction. A first metallic structure is electrically coupled with the first source region. A second metallic structure is electrically coupled with the second drain region. A third metallic structure is disposed over and electrically coupled with the first and second metallic structures. A width of the first metallic structure is substantially equal to or larger than a width of the third metallic structure.
    Type: Grant
    Filed: February 13, 2023
    Date of Patent: September 17, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ali Keshavarzi, Ta-Pen Guo, Shu-Hui Sung, Hsiang-Jen Tseng, Shyue-Shyh Lin, Lee-Chung Lu, Chung-Cheng Wu, Li-Chun Tien, Jung-Chan Yang, Ting Yu Chen, Min Cao, Yung-Chin Hou
  • Patent number: 12094950
    Abstract: Semiconductor structures and the manufacturing method thereof are disclosed. An exemplary manufacturing method includes forming a stack of a first type and a second type epitaxial layers on a frontside of a semiconductor substrate, patterning the stack to form a fin-shaped structure, depositing a dielectric layer on sidewalls of the fin-shaped structure, and recessing the dielectric layer to expose a top portion of the fin-shaped structure. A top surface of the recessed dielectric layer is above a bottom surface of the stack. The exemplary manufacturing method also includes forming a gate structure over the top portion of the fin-shaped structure, etching the semiconductor substrate from a backside of the semiconductor substrate, and etching at least a bottommost first type epitaxial layer and a bottommost second type epitaxial layer through the trench.
    Type: Grant
    Filed: December 15, 2022
    Date of Patent: September 17, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD
    Inventors: Kuo-Cheng Chiang, Yen-Ming Chen, Jung-Chien Cheng, Chih-Hao Wang, Kuan-Lun Cheng
  • Publication number: 20240304687
    Abstract: A semiconductor device and a method of fabricating the semiconductor device are disclosed. The method includes forming a polysilicon structure on a substrate, depositing a first spacer layer on the polysilicon structure, depositing a second spacer layer on the first spacer layer, forming a S/D region on the substrate, removing the second spacer layer, depositing a third spacer layer on the first spacer layer and on the S/D region, depositing an ESL on the third spacer layer, depositing an ILD layer on the etch stop layer, and replacing the polysilicon structure with a gate structure surrounding the nanostructured layer.
    Type: Application
    Filed: August 11, 2023
    Publication date: September 12, 2024
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chien Ning Yao, Chia-Hao Chang, Shih-Cheng Chen, Chih-Hao Wang, Chia-Cheng Tsai, Kuo-Cheng Chiang, Zhi-Chang Lin, Jung-Hung Chang, Tsung-Han Chuang
  • Patent number: 12087634
    Abstract: A method of forming a semiconductor structure is provided. The method includes forming a gate structure over an active region of a substrate, forming an epitaxial layer comprising first dopants of a first conductivity type over portions of the active region on opposite sides of the gate structure, the epitaxial layer, applying a cleaning solution comprising ozone and deionized water to the epitaxial layer, thereby forming an oxide layer on the epitaxial layer, forming a patterned photoresist layer over the oxide layer and the gate structure to expose a portion of the oxide layer, forming a contact region second dopants of a second conductivity type opposite the first conductivity type in the portion of the epitaxial layer not covered by the patterned photoresist layer, and forming a contact overlying the contact region.
    Type: Grant
    Filed: January 9, 2023
    Date of Patent: September 10, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ke-Ming Chen, Ting-Jung Chang, Hsin-Chen Cheng, Chih-Tsang Tseng
  • Patent number: 12087689
    Abstract: Multi-die structures and methods of fabrication are described. In an embodiment, a multi-die structure includes a first die, a second die, and die-to-die routing connecting the first die to the second die. The die-to-die interconnection may be monolithically integrated as a chip-level die-to-die routing, or external package-level die-to-die routing.
    Type: Grant
    Filed: October 17, 2023
    Date of Patent: September 10, 2024
    Assignee: Apple Inc.
    Inventors: Sanjay Dabral, Jun Zhai, Jung-Cheng Yeh, Kunzhong Hu, Raymundo Camenforte, Thomas Hoffmann
  • Patent number: 12080101
    Abstract: A system and method of mode selection face recognition with parallel CNNs are disclosed. The system includes a mode selection module, a parallel convolutional neural network module, a database module and an ID judgment module. The parallel convolutional neural network module includes several convolutional neural network units. The mode selection module can determine the facial characteristics of each facial image, and send each facial image to the convolutional nerve corresponding to its facial characteristics The results serve as a benchmark for the ID judgment module to compare and test other facial images. By using several convolutional neural network units for facial image training for different facial characteristics of the same person, the noise from other convolutional neural network units can be reduced and the similarity in the feature vector extraction stage can be improved. The resulting accuracy of face recognition will increase.
    Type: Grant
    Filed: April 5, 2022
    Date of Patent: September 3, 2024
    Inventors: Yun-Nien Huang, Chih-Tsung Shen, Hsin-Jung Cheng
  • Publication number: 20240286889
    Abstract: A method for forming a semiconductor structure includes following operations. An interconnect structure is formed over a substrate. The interconnect structure includes a top conductive layer. A dielectric structure is formed over the interconnect structure. The dielectric structure is patterned to simultaneously form a cavity and a protrusion in the cavity. A MEMS substrate is bonded to the dielectric structure to seal the cavity. The protrusion is separated from the MEMS substrate.
    Type: Application
    Filed: May 6, 2024
    Publication date: August 29, 2024
    Inventors: CHING-KAI SHEN, JUNG-KUO TU, WEI-CHENG SHEN, YI-CHUAN TENG
  • Publication number: 20240285179
    Abstract: The present invention is related to a pulse diagnosis measurement device and related method, the method including the following steps: using a processor to calculate a mean arterial pressure of an organism based on a systolic blood pressure and a diastolic blood pressure of the organism; after applying a pressure onto a pulse location of the organism and adjusting the applied pressure to a first pressure value in a pressure interval using a pulse-holding device, using a sensor to sense a blood pressure wave of the organism in a first time period, so as to generate a first pulse wave signal, wherein the pressure interval is between the diastolic blood pressure and the mean arterial pressure; and using the processor to generate a plurality of first informations of a plurality of harmonics of the blood pressure wave based on the first pulse wave signal in the first time period.
    Type: Application
    Filed: February 21, 2024
    Publication date: August 29, 2024
    Inventors: Yu-Cheng Kuo, Jung-Hsi Kuo
  • Patent number: 12074204
    Abstract: A method for forming a semiconductor structure is provided. The method includes forming a fin structure over a substrate. The fin structure includes a protection layer and alternating first and second semiconductor layers over the protection layer. The method also includes etching the fin structure to form a source/drain recess, forming a sacrificial contact in the source/drain recess, forming a source/drain feature over the sacrificial contact in the source/drain recess, removing the first semiconductor layers of the fin structure, thereby forming a plurality of nanostructures, forming a gate stack wrapping around the nanostructures, removing the substrate thereby exposing the protection layer and the sacrificial contact and replacing the sacrificial contact with a contact plug.
    Type: Grant
    Filed: July 23, 2021
    Date of Patent: August 27, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Jung-Hung Chang, Lo Heng Chang, Zhi-Chang Lin, Shih-Cheng Chen, Chien-Ning Yao, Kuo-Cheng Chiang, Chih-Hao Wang
  • Publication number: 20240282838
    Abstract: A device includes: a stack of nanostructures; a gate structure that wraps around the nanostructures; an isolation region between the stack of nanostructures and another stack of nanostructures adjacent thereto along a first direction; a source/drain region that abuts at least one of the nanostructures; and a spacer layer that is on sidewalls of the gate structure and on sidewalls of the source/drain region, the spacer layer covering an area between the source/drain region and a neighboring source/drain region of another transistor along the first direction.
    Type: Application
    Filed: June 28, 2023
    Publication date: August 22, 2024
    Inventors: Jung-Hung CHANG, Tsung-Han CHUANG, Fu-Cheng CHANG, Shih-Cheng CHEN, Chia-Cheng TSAI, Kuo-Cheng CHIANG
  • Patent number: 12068303
    Abstract: Provided are a package structure and a method of forming the same. The method includes providing a first package having a plurality of first dies and a plurality of second dies therein; performing a first sawing process to cut the first package into a plurality of second packages, wherein one of the plurality of second packages comprises three first dies and one second die; and performing a second sawing process to remove the second die of the one of the plurality of second packages, so that a cut second package is formed into a polygonal structure with the number of nodes greater than or equal to 5.
    Type: Grant
    Filed: October 5, 2023
    Date of Patent: August 20, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wei-Hung Lin, Hui-Min Huang, Chang-Jung Hsueh, Wan-Yu Chiang, Ming-Da Cheng, Mirng-Ji Lii
  • Publication number: 20240258259
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate and a first conductive structure over the semiconductor substrate. The first conductive structure has a first protruding portion extending towards the semiconductor substrate from a lower surface of the first conductive structure. The semiconductor device structure also includes a second conductive structure over the semiconductor substrate. The second conductive structure is substantially as wide as the first conductive structure, and the second conductive structure has a second protruding portion extending towards the semiconductor substrate from a lower surface of the second conductive structure. The first conductive structure is closer to a center point of the semiconductor substrate than the second conductive structure.
    Type: Application
    Filed: April 15, 2024
    Publication date: August 1, 2024
    Inventors: Hui-Min HUANG, Ming-Da CHENG, Wei-Hung LIN, Chang-Jung HSUEH, Kai-Jun ZHAN, Yung-Sheng LIN
  • Publication number: 20240259236
    Abstract: A method and system include a symbol processing block to generate log likelihood ratios (LLRs) associated with one or more data symbols. The method and system include a channel estimation (CE) module to receive the LLRs from the symbol processing block, and to process iterative CE (ItCE) for new radio (NR) based at least on reference signals and the LLRs. The CE module can process the ItCE with a granularity of one or more resource blocks (RBs) based at least on pilot resource elements (REs) and virtual pilot REs obtained from the LLRs. The CE module can process the ItCE based at least on a frequency domain orthogonal cover codes (FD-OCC) structure of the reference signals. The reference signals can be demodulation reference signals (DMRS) configured in 5G NR. The CE module can process the ItCE by updating a CE result by adding a quantity that represents a contribution obtained from virtual pilot REs.
    Type: Application
    Filed: April 19, 2023
    Publication date: August 1, 2024
    Inventors: Federico PENNA, Sili LU, Yuansheng CHENG, Jang Wook MOON, Jung Hyun BAE, Dongwoon BAI
  • Publication number: 20240258415
    Abstract: A device includes a first stack of nanostructures formed over a substrate; a second stack of nanostructures formed adjacent to the first stack; a first gate structure on the nanostructures of the first stack; a second gate structure on the nanostructures of the second stack; a first insulating wall separating the first gate structure and the second gate structure; a hard mask layer on the first gate structure and on the second gate structure; and a gate contact extending through the hard mask layer to physically and electrically contact the first gate structure.
    Type: Application
    Filed: May 3, 2023
    Publication date: August 1, 2024
    Inventors: Kuo-Cheng Chiang, Guan-Lin Chen, Jung-Chien Cheng, Shi Ning Ju, Chih-Hao Wang
  • Publication number: 20240255569
    Abstract: A voltage tracking circuit includes a first, second, third and fourth transistor. The first transistor is in a first well, the first transistor including a first source terminal and a first body terminal that are coupled to a first voltage supply. The second transistor includes a second source terminal being coupled to the first drain terminal, a second gate terminal being coupled to a pad voltage terminal and configured to receive a pad voltage. The third transistor is in a second well, and includes a third gate terminal coupled to the first voltage supply, and a third body terminal coupled to a first node. The fourth transistor includes a fourth drain terminal coupled to the third source terminal, a fourth gate terminal coupled to the third gate terminal and the first voltage supply, and a fourth source terminal coupled to the pad voltage terminal.
    Type: Application
    Filed: April 15, 2024
    Publication date: August 1, 2024
    Inventors: Hsiang-Hui CHENG, Chia-Jung CHANG
  • Patent number: 12051896
    Abstract: A device is disclosed herein. The device includes a bias generator, an ESD driver, and a logic circuit. The bias generator includes a first transistor. The ESD driver includes a second transistor and a third transistor coupled to each other in series. The logic circuit is configured to generate a logic control signal. When the first transistor is turned on by a detection signal, the first transistor is turned off.
    Type: Grant
    Filed: May 24, 2023
    Date of Patent: July 30, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Po-Lin Peng, Yu-Ti Su, Chia-Wei Hsu, Ming-Fu Tsai, Shu-Yu Su, Li-Wei Chu, Jam-Wem Lee, Chia-Jung Chang, Hsiang-Hui Cheng
  • Patent number: 12051736
    Abstract: A device includes a substrate, a first nanostructure channel above the substrate and a second nanostructure channel between the first nanostructure channel and the substrate. An inner spacer is between the first nanostructure channel and the second nanostructure channel. A gate structure abuts the first nanostructure channel, the second nanostructure channel and the inner spacer. A liner layer is between the inner spacer and the gate structure.
    Type: Grant
    Filed: August 31, 2021
    Date of Patent: July 30, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tsung-Han Chuang, Zhi-Chang Lin, Shih-Cheng Chen, Jung-Hung Chang, Chien Ning Yao, Kuo-Cheng Chiang, Chih-Hao Wang